UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 227

• Manufacturer Part Number: UPD78F9502MA-CAC-A
• Description: 8BIT MCU, 4K FLASH, 128B RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F9502MA-CAC-A

• Controller Family/series: UPD78F
• No. Of I/o's: 8
• Ram Memory Size: 128Byte
• Cpu Speed: 10MHz
• No. Of Timers: 2
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

Flash
memory
Function
Self
programming
function
FLPMC: Flash
programming
mode control
register
PFCMD: Flash
protect
command
register
PFS: Flash
status register
FLAPH,
FLAPL: Flash
address
pointers H and
L
FLAPHC,
FLAPLC: Flash
address pointer
H/L compare
registers
Details of
Function
Since the security function set via on-board/off-board programming is disabled in
self programming mode, the self programming command can be executed
regardless of the security function setting. To disable write or erase processing
during self programming, set the protect byte.
Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address
pointer H compare register (FLAPHC) to 0 before executing the self programming
command. If the value of these bits is 1 when executing the self programming
command.
Clear the value of the FLCMD register to 00H immediately before setting self-
programming mode and normal operation mode.
Cautions in the case of setting the self programming mode, refer to 14.8.2
Cautions on self programming function.
Set the CPU clock so that it is 1 MHz or more during self programming.
Execute the NOP and HALT instructions immediately after executing a specific
sequence to set self-programming mode, then execute self programming. At this
time, the HALT instruction is automatically released after 10 s (MAX.) + 2 CPU
clocks (f
If the clock of the oscillator or an external clock is selected as the system clock,
execute the NOP and HALT instructions immediately after executing a specific
sequence to set self-programming mode, wait for 8 s after releasing the HALT
status, and then execute self programming.
Clear the value of the FLCMD register to 00H immediately before setting
selfprogramming mode and normal operation mode.
Interrupt servicing cannot be executed in self-programming mode. Disable
interrupt servicing (by executing the DI instruction while MK0 and MK1 = FFH)
before executing the specific sequence that sets self-programming mode and
after executing the specific sequence that changes the mode to the normal mode.
Check FPRERR using a 1-bit memory manipulation instruction.
Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address
pointer H compare register (FLAPHC) to 0 before executing the self programming
command. If the value of these bits is 1 when executing the self programming
command.
Be sure to clear bits 4 to 7 of flash address pointer H (FLAPH) and flash address
pointer H compare register (FLAPHC) to 0 before executing the self programming
command. If the value of these bits is 1 when executing the self programming
command.
Set the number of the block subject to a block erase, verify, or blank check (same
value as FLAPH) to FLAPHC.
Clear FLAPLC to 00H when a block erase is performed, and FFH when a blank
check is performed.
Preliminary User’s Manual U18681EJ1V0UD
CPU
APPENDIX C LIST OF CAUTIONS
).
Cautions
p. 147
p. 147
p. 147
p. 148
p. 148
p. 148
p. 148
p. 148
p. 149
p. 149
p. 152
p. 152
p. 152
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