UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 90

• Manufacturer Part Number: UPD78F9502MA-CAC-A
• Description: 8BIT MCU, 4K FLASH, 128B RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F9502MA-CAC-A

• Controller Family/series: UPD78F
• No. Of I/o's: 8
• Ram Memory Size: 128Byte
• Cpu Speed: 10MHz
• No. Of Timers: 2
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

7.3
(1) Watchdog timer mode register (WDTM)
90
Address: FF48H
The watchdog timer is controlled by the following two registers.
Symbol
WDTM
This register sets the overflow time and operation clock of the watchdog timer.
This register can be set by an 7-bit memory manipulation instruction and can be read many times, but can be
written only once after reset is released.
Reset signal generation sets this register to 67H.
Watchdog timer mode register (WDTM)
Watchdog timer enable register (WDTE)
Registers Controlling Watchdog Timer
Notes 1.
Cautions 1. Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values.
WDCS4
WDCS2
0
0
1
0
0
0
0
1
1
1
1
7
0
2.
Note 1
Note 2
After reset: 67H
WDCS3
WDCS1
If “low-speed internal oscillator cannot be stopped” is specified by the option byte, this cannot
be set. The low-speed internal oscillation clock will be selected no matter what value is
written.
Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).
Figure 7-2. Format of Watchdog Timer Mode Register (WDTM)
0
1
0
0
1
1
0
0
1
1
6
1
Note 1
Note 2
WDCS0
Low-speed internal oscillation clock (f
System Clock (f
Watchdog timer operation stopped
R/W
0
1
0
1
0
1
0
1
5
1
Preliminary User’s Manual U18681EJ1V0UD
CHAPTER 7 WATCHDOG TIMER
Note 2
2
2
2
2
2
2
2
2
11
12
13
14
15
16
17
18
WDCS4
oscillation clock operation
During low-speed internal
/f
/f
/f
/f
/f
/f
/f
/f
X
RL
RL
RL
RL
RL
RL
RL
RL
)
4
(4.27 ms)
(8.53 ms)
(17.07 ms)
(34.13 ms)
(68.27 ms)
(136.53 ms)
(273.07 ms)
(546.13 ms)
Operation clock selection
WDCS3
3
Overflow time setting
RL
)
WDCS2
2
2
2
2
2
2
2
2
2
During system clock operation
13
14
15
16
17
18
19
20
/f
/f
/f
/f
/f
/f
/f
/f
X
X
X
X
X
X
X
X
(819.2 s)
(1.64 ms)
(3.28 ms)
(6.55 ms)
(13.11 ms)
(26.21 ms)
(52.43 ms)
(104.86 ms)
WDCS1
1
WDCS0
0