UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 114

• Manufacturer Part Number: UPD78F9502MA-CAC-A
• Description: 8BIT MCU, 4K FLASH, 128B RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F9502MA-CAC-A

• Controller Family/series: UPD78F
• No. Of I/o's: 8
• Ram Memory Size: 128Byte
• Cpu Speed: 10MHz
• No. Of Timers: 2
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

programs at the address written in addresses 0000H and 0001H when the reset signal is generated.
circuit voltage detection, and each item of hardware is set to the status shown in Table 10-1. Each pin is high
impedance during reset signal generation or during the oscillation stabilization time just after reset release, except for
P130, which is low-level output.
reset is released and the CPU starts program execution after referencing the option byte. A reset generated by the
watchdog timer source is automatically released after the reset, and the CPU starts program execution after
referencing the option byte. (see Figures 10-2 to 10-4). Reset by POC and LVI circuit power supply detection is
automatically released when V
referencing the option byte (see CHAPTER 11 POWER-ON-CLEAR CIRCUIT and CHAPTER 12 LOW-VOLTAGE
DETECTOR).
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The following four operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer overflows
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)
External and internal resets have no functional differences. In both cases, program execution starts from the
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI
When a low level is input to the RESET pin, a reset occurs, and when a high level is input to the RESET pin, the
Cautions 1. For an external reset, input a low level for 2 s or more to the RESET pin.
2. During reset signal generation, the system clock and low-speed internal oscillation clock
3. When the RESET pin is used as an input-only port pin (P34), the
stop oscillating.
78F9502 are reset if a low level is input to the RESET pin after reset is released by the POC
circuit and before the option byte is referenced again. The reset status is retained until a
high level is input to the RESET pin.
DD
> V
POC
CHAPTER 10 RESET FUNCTION
Preliminary User’s Manual U18681EJ1V0UD
or V
DD
> V
LVI
after the reset, and the CPU starts program execution after
PD78F9500, 78F9501,