UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 195

• Manufacturer Part Number: UPD78F9502MA-CAC-A
• Description: 8BIT MCU, 4K FLASH, 128B RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F9502MA-CAC-A

• Controller Family/series: UPD78F
• No. Of I/o's: 8
• Ram Memory Size: 128Byte
• Cpu Speed: 10MHz
• No. Of Timers: 2
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

Remark
CMP
ADDW
SUBW
CMPW
INC
DEC
INCW
DECW
ROR
ROL
RORC
ROLC
SET1
CLR1
SET1
CLR1
NOT1
Mnemonic
One instruction clock cycle is one CPU clock cycle (f
(PCC).
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
AX, #word
AX, #word
AX, #word
r
saddr
r
saddr
rp
rp
A, 1
A, 1
A, 1
A, 1
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
CY
CY
Operand
CHAPTER 15 INSTRUCTION SET OVERVIEW
Preliminary User’s Manual U18681EJ1V0UD
Bytes
2
3
2
2
3
1
2
3
3
3
2
2
2
2
1
1
1
1
1
1
3
3
2
3
2
3
3
2
3
2
1
1
1
Clocks
10
10
4
6
4
4
8
6
6
6
6
6
4
4
4
4
4
4
2
2
2
2
6
6
4
6
6
6
4
6
2
2
2
(saddr)
A
A
AX, CY
AX, CY
AX
r
(saddr)
r
(saddr)
rp
rp
(CY, A
(CY, A
(CY
(CY
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
CY
CY
CY
A
A
A
A
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
r + 1
r
word
rp + 1
rp
7
0
1
0
CY
A
A
1
CPU
1
0
0
7
1
0
byte
, A
, A
1
(saddr) + 1
(saddr)
AX + word
AX
1
0
A
A
) selected by the processor clock control register
1
0
0
7
7
0
, A
, A
1
0
m 1
m+1
word
CY, A
CY, A
Operation
1
A
A
m 1
m+1
m
m
)
)
1
1
A
A
m
m
)
)
1
1
Z
Flag
AC CY
195
1
0