UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 34

• Manufacturer Part Number: UPD78F9502MA-CAC-A
• Description: 8BIT MCU, 4K FLASH, 128B RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F9502MA-CAC-A

• Controller Family/series: UPD78F
• No. Of I/o's: 8
• Ram Memory Size: 128Byte
• Cpu Speed: 10MHz
• No. Of Timers: 2
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

3.2.3 Special function registers (SFRs)
bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function register
type.
34
Unlike the general-purpose registers, each special function register has a special function.
The special function registers are allocated to the 256-byte area FF00H to FFFFH.
The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and
Each manipulation bit unit can be specified as follows.
Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows:
1-bit manipulation
Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This
manipulation can also be specified with an address and bit.
8-bit manipulation
Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
manipulation can also be specified with an address.
16-bit manipulation
Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When specifying
an address, describe an even address.
Symbol
Indicates the addresses of the implemented special function registers. It is defined as a reserved word in the
RA78K0S, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S. Therefore, these
symbols can be used as instruction operands if an assembler or integrated debugger is used.
R/W
Indicates whether the special function register can be read or written.
R/W: Read/write
R:
W:
Number of bits manipulated simultaneously
Indicates the bit units (1, 8, and 16) in which the special function register can be manipulated.
After reset
Indicates the status of the special function register when a reset is input.
Read only
Write only
Preliminary User’s Manual U18681EJ1V0UD
CHAPTER 3 CPU ARCHITECTURE
This