UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 31

8BIT MCU, 4K FLASH, 128B RAM, SMD

UPD78F9502MA-CAC-A

Manufacturer Part Number
UPD78F9502MA-CAC-A
Description
8BIT MCU, 4K FLASH, 128B RAM, SMD
Manufacturer
NEC
Datasheet

Specifications of UPD78F9502MA-CAC-A

Controller Family/series
UPD78F
No. Of I/o's
8
Ram Memory Size
128Byte
Cpu Speed
10MHz
No. Of Timers
2
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
4KB
Oscillator Type
External, Internal
(a) Interrupt enable flag (IE)
(b) Zero flag (Z)
(c) Auxiliary carry flag (AC)
(d) Carry flag (CY)
This flag controls interrupt request acknowledge operations of the CPU.
When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests are disabled.
When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with
an interrupt mask flag for various interrupt sources.
This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI
instruction execution.
When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all
other cases.
This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It
stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit
operation instruction execution.
Preliminary User’s Manual U18681EJ1V0UD
CHAPTER 3 CPU ARCHITECTURE
31

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