UPD78F9502MA-CAC-A NEC, UPD78F9502MA-CAC-A Datasheet - Page 194

• Manufacturer Part Number: UPD78F9502MA-CAC-A
• Description: 8BIT MCU, 4K FLASH, 128B RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F9502MA-CAC-A

• Controller Family/series: UPD78F
• No. Of I/o's: 8
• Ram Memory Size: 128Byte
• Cpu Speed: 10MHz
• No. Of Timers: 2
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

194
Remark
SUBC
AND
OR
XOR
Mnemonic
One instruction clock cycle is one CPU clock cycle (f
(PCC).
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
Operand
CHAPTER 15 INSTRUCTION SET OVERVIEW
Preliminary User’s Manual U18681EJ1V0UD
Bytes
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
Clocks
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
A, CY
(saddr), CY
A, CY
A, CY
A, CY
A, CY
A, CY
A
(saddr)
A
A
A
A
A
A
(saddr)
A
A
A
A
A
A
(saddr)
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
CPU
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
A
A
A
A
A
A
(saddr)
(saddr)
(saddr)
) selected by the processor clock control register
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
(saddr)
CY
CY
Operation
CY
byte
byte
byte
CY
CY
byte
CY
CY
Z
Flag
AC CY