NS32FX164AV-25 National Semiconductor, NS32FX164AV-25 Datasheet - Page 2

• Manufacturer Part Number: NS32FX164AV-25
• Description: IC IMAGING COMM SGNL PROC PLCC68
• Manufacturer: National Semiconductor

Specifications of NS32FX164AV-25

• Processor Type: Advanced Imaging/Communications Signal Processor SIAP™
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NS32FX164AV-25; Q1284286

1 0 PRODUCT INTRODUCTION
2 0 ARCHITECTURAL DESCRIPTION
3 0 FUNCTIONAL DESCRIPTION
1 1 NS32FX164 Special Features
2 1 Register Set
2 2 Memory Organization
2 3 Modular Software Support
2 4 Instruction Set
2 5 Graphics Support
3 1 Instruction Execution
3 2 Exception Processing
2 1 1 General Purpose Registers
2 1 2 Address Registers
2 1 3 Processor Status Register
2 1 4 Configuration Register
2 1 5 DSP Module Registers
2 2 1 Address Mapping
2 4 1 General Instruction Format
2 4 2 Addressing Modes
2 4 3 Instruction Set Summary
2 5 1 Frame Buffer Addressing
2 5 2 BITBLT Fundamentals
2 5 3 Graphics Support Instructions
3 1 1 Operating States
3 1 2 Instruction Endings
3 1 3 Slave Processor Instructions
3 2 1 Exception Acknowledge Sequence
2 5 2 1 Frame Buffer Architecture
2 5 2 2 Bit Alignment
2 5 2 3 Block Boundaries and Destination
2 5 2 4 BITBLT Directions
2 5 2 5 BITBLT Variations
2 5 3 1 BITBLT (BIT-aligned BLock Transfer) 23
2 5 3 2 Pattern Fill
2 5 3 3 Data Compression Expansion and
3 1 2 1 Completed Instructions
3 1 2 2 Suspended Instructions
3 1 2 3 Terminated Instructions
3 1 2 4 Partially Completed Instructions
3 1 3 1 Slave Processor Protocol
3 1 3 2 Floating-Point Instructions
Masks
Magnify
2 5 3 3 1 Magnifying Compressed
Data
Table of Contents
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3 3 Debugging Support
3 4 DSP Module
3 2 2 Returning from an Exception Service
3 2 3 Maskable Interrupts
3 2 4 Non-Maskable Interrupt
3 2 5 Traps
3 2 6 Priority among Exceptions
3 2 7 Exception Acknowledge Sequences Detailed
3 3 1 Instruction Tracing
3 4 1 Programming Model
3 4 2 RAM Organization and Data Types
3 4 3 Command List Format
3 4 4 CPU Core Interface
3 4 5 DSPM Instruction Set
Procedure
3 2 3 1 Non-Vectored Mode
3 2 3 2 Vectored Mode Non-Cascaded
3 2 3 3 Vectored Mode Cascaded Case
Flow
3 2 7 1 Maskable Non-Maskable Interrupt
3 2 7 2 SLAVE ILL SVC DVZ FLG BPT UND
3 2 7 3 Trace Trap Sequence
3 4 2 1 Integer Values
3 4 2 2 Aligned-Integer Values
3 4 2 3 Real Values
3 4 3 4 Aligned-Real Values
3 4 2 5 Extended Precision Real Values
3 4 2 6 Complex Values
3 4 4 1 Synchronization of Parallel Operation 42
3 4 4 2 DSPM RAM Organization
3 4 5 1 Conventions
3 4 5 2 Type Casting
3 4 5 3 General Notes
3 4 5 4 Load Register Instructions
3 4 5 5 Store Register Instructions
3 4 5 6 Adjust Register Instructions
3 4 5 7 Flow Control Instructions
3 4 5 8 Internal Memory Move Instructions
3 4 5 9 External Memory Move Instructions
3 4 5 10 Arithmetic Logical Instructions
3 4 5 11 Multiply-and-Accumulate
3 4 5 12 Multiply-and-Add Instructions
3 4 5 13 Clipping and Min Max Instructions
3 4 5 14 Special Instructions
Case
Sequence
Trap Sequence
Instructions
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