NS32FX164AV-25 National Semiconductor, NS32FX164AV-25 Datasheet - Page 68

• Manufacturer Part Number: NS32FX164AV-25
• Description: IC IMAGING COMM SGNL PROC PLCC68
• Manufacturer: National Semiconductor

Specifications of NS32FX164AV-25

• Processor Type: Advanced Imaging/Communications Signal Processor SIAP™
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NS32FX164AV-25; Q1284286

3 0 Functional Description
3 5 5 9 Bus Access Control
The NS32FX164 CPU has the capability of relinquishing its
control of the bus upon request from a DMA controller or
another CPU This capability is implemented by means of
the HOLD (Hold Request) and HLDA (Hold Acknowledge)
pins By asserting HOLD low an external device requests
access to the bus On receipt of HLDA from the CPU the
device may perform bus cycles as the CPU at this point has
Byte 7
Other Bus Cycles (Instruction Prefetch or Slave) can occur here
Byte 7
Other Bus Cycles (Instruction Prefetch or Slave) can occur here
Cycle
1
2
3
4
1
2
3
4
5
6
1
2
1
1
1
2
3
Even Word
Even Word
Even Word
Even Word
Odd Byte
Even Word
Even Byte
Odd Byte
Even Word
Even Byte
Odd Byte
Even Byte
Even Word
Even Word
Odd Byte
Even Word
Even Byte
Byte 6
Byte 6
Type
Byte 5
A
A
A
A
Byte 5
A
A
A
A
A
A
Address
A
A
A
A
A
A
A
a
a
a
a
a
a
a
a
a
a
a
a
2
4
6
1
3
4
5
7
1
2
1
3
Byte 4
Byte 4
Byte 3
Byte 3
B Even Double-Word Access Sequence
HBE
C Odd Double-Word Access Sequence
D Even Quad-Word Access Sequence
E Odd Quad-Word Access Sequence
0
1
0
0
0
0
1
TABLE 3-6 Data Access Sequences
(Continued)
Byte 3
Byte 3
A Odd Word Access Sequence
0
0
0
0
0
0
1
0
0
1
Byte 2
Byte 2
A0
68
1
0
0
0
1
0
0
Byte 2
Byte 2
0
0
0
0
1
0
0
1
0
0
set AD0– AD15 A16– A23 and HBE to the TRI-STATE
condition and has switched ADS and DDIN to the input
mode ALE is asserted in T4 and stays high during the time
the bus is granted The CPU now monitors ADS and DDIN
from the external device to generate the relevant strobe
signals (i e TSO DBE RD or WR) To return control of the
bus to the CPU the device sets HOLD inactive and the
CPU acknowledges it by setting HLDA inactive
Byte 0
Don’t Care
Byte 1
Byte 3
Byte 0
Byte 2
Don’t Care
Byte 1
Byte 3
Byte 5
Byte 7
Byte 0
Byte 2
Don’t Care
Byte 4
Byte 6
Don’t Care
High Bus
Byte 1
Byte 1
Byte 1
Byte 1
Byte 1
Don’t Care
Byte 1
Byte 0
Byte 2
Don’t Care
Byte 1
Byte 3
Byte 0
Byte 2
Byte 4
Byte 6
Don’t Care
Byte 1
Byte 3
Don’t Care
Byte 5
Byte 7
Low Bus
Byte 0
Byte 0
Byte 0
Byte 0
Byte 0
A
A
A
A
A