NS32FX164AV-25 National Semiconductor, NS32FX164AV-25 Datasheet - Page 57

• Manufacturer Part Number: NS32FX164AV-25
• Description: IC IMAGING COMM SGNL PROC PLCC68
• Manufacturer: National Semiconductor

Specifications of NS32FX164AV-25

• Processor Type: Advanced Imaging/Communications Signal Processor SIAP™
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NS32FX164AV-25; Q1284286

3 0 Functional Description
Type
Tolerance
Stability
Resonance
Maximum Series Resistance
Maximum Shunt Capacitance
3 5 3 Power Save Mode
The NS32FX164 provides a power save feature that can be
used to significantly reduce the power consumption at times
when the computational demand decreases The device
uses the clock signal at the OSCIN pin to derive the internal
clock as well as the external signals CTTL and FCLK The
frequency of these clock signals is affected by the clock
scaling factor Scaling factors of 1 2 4 or 8 can be select-
ed by properly setting the C- and M-bits in the CFG register
The power save mode should not be used to reduce the
clock frequency below the minimum frequency required by
the CPU
Upon reset both C and M are set to zero thus maximum
clock rate is selected
Due to the fact that the C- and M-bits are programmed by
the SETCFG instruction the power save feature can only be
controlled by programs running in supervisor mode
The following table shows the C- and M-bit settings for the
various scaling factors and the resulting supply current for a
crystal frequency of 50 MHz
3 5 4 Resetting
The RSTI input pin is used to reset the NS32FX164 The
CPU samples RSTI on the falling edge of CTTL
Whenever a low level is detected the CPU responds imme-
diately Any instruction being executed is terminated any
results that have not yet been written to memory are dis-
carded and any pending interrupts and traps are eliminated
The internal latch for the edge-sensitive NMI signal is
cleared The DSP module ST register is set to 0
Frequency
30 MHz
40 MHz or 50 MHz
C
0
0
1
1
(MHz)
30
30
40
50
Clock Scaling Factor vs Supply Current
M
0
1
0
1
Specifications Crystal Characteristics
TABLE 3-3 External Oscillator
(k )
180
180
150
150
R1
Scaling
Factor
1
2
4
8
R C and L Values
( )
R2
51
51
51
51
(pF)
C1
20
20
20
20
Frequency
CPU Clock
12 5 MHz
6 25 MHz
3 13 MHz
25 MHz
0 01% from 0 C to
(pF)
C2
Third Overtone (Parallel)
20
20
20
20
Fundamental (Parallel)
800–1300
800–1300
800–1300
0 005% at
(pF)
(Continued)
C3
Typical I
at
200 mA
120 mA
80 mA
55 mA
a
5V
AT-Cut
a
a
( H)
CC
25 C
70 C
3 3
1 8
1 1
50
7 pF
L
57
On application of power RSTI must be held low for at least
50 s after V
voltages are completely stable before operation Whenever
a Reset is applied it must also remain active for not less
than 64 CTTL cycles See Figures 3-18 and 3-19
While in the Reset state the CPU drives the signals ADS
IAS RD WR DBE TSO BPU IOUT and DDIN inactive
AD0– AD15 A16 – A23 and SPC are floated ALE is HIGH
and the state of all other output signals is undefined
The internal CPU clock and CTTL run at half the frequency
of the signal on the OSCIN pin
The HOLD signal must be kept inactive After the RSTI sig-
nal is driven high the CPU will stay in the reset condition for
approximately 8 clock cycles and then it will begin execution
at address 0
The PSR is reset to 0 The CFG C- and M-bits are reset to 0
FCLK runs at the same frequency as OSCIN NMI is en-
abled to allow Non-Maskable Interrupts The following con-
ditions are present after reset due to the PSR being reset to
0
Tracing is disabled
Supervisor mode is enabled
Supervisor stack space is used when the TOS addressing
mode is indicated
No trace traps are pending
Only NMI is enabled Maskable interrupts are disabled
BPU is inactive high
The Clock Scaling Factor is set to 1 refer to Section 3 5 3
Note that vector non-vectored interrupts have not been se-
lected While interrupts are disabled a SETCFG I instruc-
tion must be executed to enable vectored interrupts If non-
vectored interrupts are required a SETCFG without the I
must be executed
The presence absence of the NS32081 NS32181 or
NS32381 has also not been declared If there is a Floating-
Point Unit a SETCFG F instruction must be executed If
there is no floating-point unit a SETCFG without the F
must be executed
FIGURE 3-18 Power-On Reset Requirements
FIGURE 3-19 General Reset Timing
CC
is stable This is to ensure that all on-chip
TL EE 11267– 30
TL EE 11267– 31