NS32FX164AV-25 National Semiconductor, NS32FX164AV-25 Datasheet - Page 44

• Manufacturer Part Number: NS32FX164AV-25
• Description: IC IMAGING COMM SGNL PROC PLCC68
• Manufacturer: National Semiconductor

Specifications of NS32FX164AV-25

• Processor Type: Advanced Imaging/Communications Signal Processor SIAP™
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NS32FX164AV-25; Q1284286

3 0 Functional Description
aligned real
extended
complex
vector ptr
repeat reg
param reg
eabr reg
real acc
complex acc A 68-bit value inside the complex accumu-
3 4 5 3 General Notes
The values of the EABR PARAM X Y and Z registers are
not changed by the execution of the command list
Some instructions use the accumulator as a temporary reg-
ister and therefore destroy its contents In general the user
should assume that the contents of the accumulator are
unpredictable after an instruction terminates unless stated
otherwise in the notes section following that instruction’s
formal specification
Non-complex instructions that use the accumulator can use
either the real or the imaginary parts or both In general
when an integer or real data type is to be read it is taken
from the real part An extended-precision real data type is
taken from the imaginary part When a non-complex data
type is loaded into the accumulator (by the LEA instruction
or within other instructions prior to saving it into memory) it
is written to both real and imaginary parts
Rounding is implemented by copying PARAM RND into bit
position 14 of both the real and the imaginary part of the
accumulator performing the requested operation and trun-
cating the contents of the accumulator upon storing results
to memory In Multiply-and-Add instructions and some of the
special instructions this is done transparently on each vec-
tor element iteration In Multiply-and-Accumulate instruc-
tions when PARAM CLR is ‘‘0’’ the previous content of the
accumulator is used so that rounding control is actually per-
formed when the accumulator is first loaded and not when
the multiply operations is executed On the other hand if
PARAM CLR is ‘‘1’’ the PARAM RND value is copied into
bit 14 of the cleared accumulator so that rounding control is
done at the same time that the multiply operation is execut-
ed
Rounding is performed only for real aligned-real and com-
plex data types In operations on complex operands the
order of accumulation is as follows the result of the multipli-
cation with the real part of the X operand is added first to
the accumulator and only then the result of the multiplica-
tion with the imaginary part of the X operand is added
In general the X Y and Z vectors can overlap However
because of the pipelined structure of the DSPM datapath
the user must verify that a value written into the DSPM inter-
nal memory will not be used in the same vector instruction
as a source operand for the next 8 iterations in all instruc-
tions except VCPOLY In VCPOLY Y 0 cannot be over-rid-
den at all
An aligned real value as described in Sec-
tion 3 4 2 4
An extended-precision real value as de-
scribed in Section 3 4 2 5
A complex value as described in Section
3 4 2 6
A valid value for X Y and Z registers
A valid value for REPEAT register
A valid value for PARAM register
A valid value for EABR register
A 34-bit value inside either the real part or
the imaginary part of the accumulator
lator
(Continued)
44
The description below specifies the encoding of each DSPM
instruction All other values are reserved for future use Any
attempt to execute any reserved instructions will terminate
execution of the command list issue an NMI request and
set NMISTAT UND to ‘‘1’’ In this case the contents of the
EXT and DSPMASK remain unchanged but the contents of
the Accumulator and OVF may change
3 4 5 4 Load Register Instructions
LX Load X Vector Pointer
The LX instruction loads the double-word at aligned addr
into the X register
Syntax
LX aligned addr
Operation
Notes The value at mem aligned addr
LY Load Y Vector Pointer
The LY instruction loads the double-word at aligned addr
into the Y register
Syntax
LY aligned addr
Operation
Notes The value at mem aligned addr
LZ Load Z Vector Pointer
The LZ instruction loads the double-word at aligned addr
into the Z register
Syntax
LZ aligned addr
Operation
Notes The value at mem aligned addr
15
15
15
X
Y
Z
specification format
Accumulator is not affected
specification format
Accumulator is not affected
specification format
Accumulator is not affected
(vector ptr) mem aligned addr
(vector ptr) mem aligned addr
(vector ptr) mem aligned addr
00010
00011
00100
11 10
11 10
11 10
should conform to vector pointer
should conform to vector pointer
should conform to vector pointer
aligned addr
aligned addr
aligned addr
0
0
0