NS32FX164AV-25 National Semiconductor, NS32FX164AV-25 Datasheet - Page 35

• Manufacturer Part Number: NS32FX164AV-25
• Description: IC IMAGING COMM SGNL PROC PLCC68
• Manufacturer: National Semiconductor

Specifications of NS32FX164AV-25

• Processor Type: Advanced Imaging/Communications Signal Processor SIAP™
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NS32FX164AV-25; Q1284286

Figure 3-4 illustrates the position of the Cascade Table To
3 0 Functional Description
3 2 3 2 Vectored Mode Non-Cascaded Case
In the Vectored mode the CPU uses an Interrupt Control
Unit (ICU) to prioritize up to 16 interrupt requests Upon re-
ceipt of an interrupt request on the INT pin the CPU per-
forms an ‘‘Interrupt Acknowledge Master’’ bus cycle read-
ing a vector value from the low-order byte of the Data Bus
This vector is then used as an index into the Dispatch Table
in order to find the External Procedure Descriptor for the
proper interrupt service procedure The service procedure
eventually returns via the Return from Interrupt (RETI) in-
struction which performs an End of Interrupt bus cycle in-
forming the ICU that it may re-prioritize any interrupt re-
quests still pending The ICU provides the vector number
again which the CPU uses to determine whether it needs
also to inform a Cascaded ICU
In a system with only one ICU (16 levels of interrupt) the
vectors provided must be in the range of 0 through 127 that
is they must be positive numbers in eight bits By providing
a negative vector number an ICU flags the interrupt source
as being a Cascaded ICU (see below)
Note During a return from interrupt the CPU looks at Bit 7 of the vector
3 2 3 3 Vectored Mode Cascaded Case
In order to allow up to 256 levels of interrupt provision is
made both in the CPU and in the NS32202 Interrupt Control
Unit (ICU) to transparently support cascading Figure 3-10
shows a typical cascaded configuration Note that the Inter-
rupt output from a Cascaded ICU goes to an Interrupt Re-
quest input of the Master ICU which is the only ICU which
drives the CPU INT pin
In a system which uses cascading two tasks must be per-
formed upon initialization
1) For each Cascaded ICU in the system the Master ICU
2) A Cascade Table must be established in memory The
find the Cascade Table entry for a Cascaded ICU take its
Master ICU line number (0 to 15) and subtract 16 from it
giving an index in the range
by 4 and add the resulting negative number to the contents
of the INTBASE Register The 32-bit entry at this address
must be set to the address of the Hardware Vector Register
of the Cascaded ICU This is referred to as the ‘‘Cascade
Address ’’
must be informed of the line number (0 to 15) on which it
receives the cascaded requests
Cascade Table is located in a NEGATIVE direction from
the location indicated by the CPU Interrupt Base (INT-
BASE) Register Its entries are 32-bit addresses pointing
to the Vector Registers of each of up to 16 Cascaded
ICUs
number from the master ICU If Bit 7 is 0 bits 0 through 6 are ignored
b
16 to
b
1 Multiply this value
(Continued)
35
Upon receipt of an interrupt request from a Cascaded ICU
the Master ICU interrupts the CPU and provides the nega-
tive Cascade Table index instead of a (positive) vector num-
ber The CPU seeing the negative value uses it as an index
into the Cascade Table and reads the Cascade Address
from the referenced entry Applying this address the CPU
performs an ‘‘Interrupt Acknowledge Cascaded’’ bus cycle
reading the final vector value This vector is interpreted by
the CPU as an unsigned byte and can therefore be in the
range of 0 through 255
In returning from a Cascaded interrupt the service proce-
dure executes the Return from Interrupt (RETI) instruction
as it would for any Maskable Interrupt The CPU performs
an ‘‘End of Interrupt Master’’ bus cycle whereupon the
Master ICU again provides the negative Cascaded Table
index The CPU seeing a negative value uses it to find the
corresponding Cascade Address from the Cascade Table
Applying this address it performs an ‘‘End of Interrupt Cas-
caded’’ bus cycle informing the Cascaded ICU of the com-
pletion of the service routine The byte read from the Cas-
caded ICU is discarded
Note If an interrupt must be masked off the CPU can do so by setting the
corresponding bit in the Interrupt Mask Register of the Interrupt Con-
troller However if an interrupt is set pending during the CPU instruc-
tion that masks off that interrupt the CPU may still perform an inter-
rupt acknowledge cycle following that instruction since it might have
sampled the INT line before the ICU deasserted it This could cause
the ICU to provide an invalid vector To avoid this problem the above
operation should be performed with the CPU interrupt disabled
FIGURE 3-9 Interrupt Control Unit
Connections (16 Levels)
TL EE 11267– 22