NS32FX164AV-25 National Semiconductor, NS32FX164AV-25 Datasheet - Page 45

• Manufacturer Part Number: NS32FX164AV-25
• Description: IC IMAGING COMM SGNL PROC PLCC68
• Manufacturer: National Semiconductor

Specifications of NS32FX164AV-25

• Processor Type: Advanced Imaging/Communications Signal Processor SIAP™
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NS32FX164AV-25; Q1284286

addr into the A accumulator as a complex value
aligned addr into the PARAM register
aligned addr into the REPEAT register
3 0 Functional Description
LA Load Accumulator
The LA instruction loads the complex value at aligned
Syntax
LA aligned addr
Operation
Notes The real and imaginary parts are placed in bits 15 through 30 of the
LEA Load Extended Accumulator
The LEA instruction loads the accumulator with the extend-
ed value specified by X 0
Both the real and the imaginary parts of the accumulator are
loaded
Syntax
EXEC LEA
Operation
Note Bits 1 through 31 of the memory location are read into bit positions 0
LPARAM Load Parameters Register
The LPARAM instruction loads the double-word at
Syntax
LPARAM aligned addr
Operation
Notes The value at mem aligned addr should conform to this register
LREPEAT Load Repeat Register
The LREPEAT instruction loads the double-word at
Syntax
LREPEAT aligned addr
15
15
15
(complex) A
extended X
A
PARAM
through 30 of the accumulator
real and imaginary parts of the accumulator
When PARAM RND is set to ‘‘1’’ bit 14 of the real and imaginary
parts is set to ‘‘1’’ in order to implement rounding upon subsequent
additions into the accumulator Otherwise it is cleared to ‘‘0’’
format The value written into PARAM LENGTH must be greater
then 0
Accumulator is not affected
(extended) X 0
00101
10000
00000
(param reg) mem aligned addr
(complex) mem aligned addr
11 10
11 10
11 10
101 0011 0011
aligned addr
aligned addr
(Continued)
0
0
0
45
Operation
Notes The value at mem aligned addr
LEABR Load External Address Base Register
The
mem aligned addr
Syntax
LEABR aligned addr
Operation
Notes The value at mem aligned addr
3 4 5 5 Store Register Instructions
SX Store X Vector Pointer
The SX instruction stores the contents of the X register into
the double-word at aligned addr
Syntax
SX aligned addr
Operation
Note Accumulator is not affected
SXL Store X Vector Pointer Lower Half
The SXL instruction stores the contents of the lower-half of
the X register into the word at mem addr
Syntax
SXL addr
Operation
Note Accumulator is not affected
15
15
15
15
REPEAT
EABR
(vector ptr) mem aligned addr
mem aligned addr
register format
Accumulator is not affected
specification format that is bit positions 0 through 16 must be speci-
fied as ‘‘0’
Accumulator is not affected
LEABR
00110
00111
01010
11100
(eabr reg) mem aligned addr
(repeat reg) mem aligned addr
instruction
into the EABR register
11 10
11 10
11 10
11 10
loads
X low
should conform to vector pointer
should conform to the REPEAT
the
aligned addr
aligned addr
aligned addr
addr
double-word
X
0
0
0
0
at