NS32FX164AV-25 National Semiconductor, NS32FX164AV-25 Datasheet - Page 3

• Manufacturer Part Number: NS32FX164AV-25
• Description: IC IMAGING COMM SGNL PROC PLCC68
• Manufacturer: National Semiconductor

Specifications of NS32FX164AV-25

• Processor Type: Advanced Imaging/Communications Signal Processor SIAP™
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NS32FX164AV-25; Q1284286

4 0 DEVICE SPECIFICATIONS
FIGURE 1-1
FIGURE 2-1
FIGURE 2-2
FIGURE 2-3
FIGURE 2-4
FIGURE 2-5
FIGURE 2-6
FIGURE 2-7
FIGURE 2-8
FIGURE 2-9
FIGURE 2-10 REPEAT Register Format
FIGURE 2-11 EXT Register Format
FIGURE 2-12 CLSTAT Register Format
FIGURE 2-13 DSPINT and DSPMASK Register Format
FIGURE 2-14 NMISTAT Register Format
FIGURE 2-15 NS32FX164 Address Mapping
FIGURE 2-16 NS32FX164 Run-Time Environment
FIGURE 2-17 General Instruction Format
FIGURE 2-18 Index Byte Format
FIGURE 2-19 Displacement Encodings
FIGURE 2-20 Correspondence between Linear and Cartesian Addressing
FIGURE 2-21 32-Pixel by 32-Scan Line Frame Buffer
FIGURE 2-22 Overlapping BITBLT Blocks
FIGURE 2-23 BB Instructions Format
FIGURE 2-24 BITWT Instruction Format
FIGURE 2-25 EXTBLT Instruction Format
FIGURE 2-26 MOVMPi Instruction Format
3 5 System Interface
4 1 NS32FX164 Pin Descriptions
3 5 1 Power and Grounding
3 5 2 Clocking
3 5 3 Power Save Mode
3 5 4 Resetting
3 5 5 Bus Cycles
4 1 1 Supplies
4 1 2 Input Signals
4 1 3 Output Signals
4 1 4 Input-Output Signals
3 5 5 1 Bus Status
3 5 5 2 Basic Read and Write Cycles
3 5 5 3 Cycle Extension
3 5 5 4 Instruction Fetch Cycles
3 5 5 5 Interrupt Control Cycles
3 5 5 6 Special Bus Cycles
3 5 5 7 Slave Processor Bus Cycles
3 5 5 8 Data Access Sequences
3 5 5 9 Bus Access Control
3 5 5 10 Instruction Status
CPU Block Diagram
NS32FX164 Internal Registers
Processor Status Register (PSR)
Configuration Register (CFG)
DSP Module Registers Address Map
Accumulator Format
X Y Z Registers Format
EABR Register Format
OVF Register Format
PARAM Register Format
Table of Contents
List of Figures
55
55
56
57
57
58
58
58
62
63
64
65
65
67
68
71
71
71
71
71
71
72
3
APPENDIX A INSTRUCTION FORMATS
APPENDIX B INSTRUCTION EXECUTION TIMES
4 2 Absolute Maximum Ratings
4 3 Electrical Characteristics
4 4 Switching Characteristics
B 1 Basic and Floating-Point Instructions
B 2 Special Graphics Instructions
B 3 DSPM Instructions
(Continued)
4 4 1 Definitions
4 4 2 Timing Tables
4 4 3 Timing Diagrams
B 1 1 Equations
B 1 2 Notes on Table Use
B 1 3 Calculation of the Execution Time TEX for Basic
B 1 4 Calculation of the Execution Time TEX for
B 2 1 Execution Time Calculation for Special
4 4 2 1 Output Signals Internal Propagation
4 4 2 2 Input Signal Requirements
Instructions
Floating-Point Instructions
Graphics Instructions
Delays
100
74
74
74
74
75
75
77
79
89
92
92
92
93
93
93
99
99
10
10
10
10
11
11
11
11
12
13
13
13
14
20
21
22
23
24
24
24
1
7
8
9
9
9
9