NS32FX164AV-25 National Semiconductor, NS32FX164AV-25 Datasheet - Page 21

• Manufacturer Part Number: NS32FX164AV-25
• Description: IC IMAGING COMM SGNL PROC PLCC68
• Manufacturer: National Semiconductor

Specifications of NS32FX164AV-25

• Processor Type: Advanced Imaging/Communications Signal Processor SIAP™
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NS32FX164AV-25; Q1284286

2 0 Architectural Description
2 5 2 1 Frame Buffer Architecture
There are two basic types of frame buffer architectures
plane-oriented or pixel-oriented BITBLT takes advantage of
the plane-oriented frame buffer architecture’s attribute of
multiple adjacent pixels-per-word facilitating the movement
of large blocks of data The source and destination starting
addresses are expressed as pixel addresses The width and
height of the block to be moved are expressed in terms of
pixels and scan lines The source block may start and end
at any bit position of any word and the same applies for the
destination block
2 5 2 2 Bit Alignment
Before a logical operation can be performed between the
source and the destination data the source data must first
be bit aligned to the destination data In Figure 2-21 the
source data needs to be shifted three bits to the right in
order to align the first pixel (i e the pixel at the top left
corner) in the source data block to the first pixel in the desti-
nation data block
2 5 2 3 Block Boundaries and Destination Masks
Each BITBLT destination scan line may start and end at any
bit position in any data word The neighboring bits (bits shar-
ing the same word address with any words in the destination
data block but not a part of the BITBLT rectangle) of the
BITBLT destination scan line must remain unchanged after
the BITBLT operation
FIGURE 2-21 32-Pixel by 32-Scan Line Frame Buffer
(Continued)
21
Due to the plane-oriented frame buffer architecture all
memory operations must be word-aligned In order to pre-
serve the neighboring bits surrounding the BITBLT destina-
tion block both a left mask and a right mask are needed for
all the leftmost and all the rightmost data words of the desti-
nation block The left mask and the right mask both remain
the same during a BITBLT operation
The following example illustrates the bit alignment require-
ments In this example the memory data path is 16 bits
wide Figure 2-21 shows a 32 pixel by 32 scan line frame
buffer which is organized as a long bit stream which wraps
around every two words (32 bits) The origin (top left corner)
of the frame buffer starts from the lowest word in memory
(word address 00 (hex))
Each word in the memory contains 16 bits D0 – D15 The
least significant bit of a memory word D0 is defined as the
first displayed pixel in a word In this example BITBLT ad-
dresses are expressed as pixel addresses relative to the
origin of the frame buffer The source block starting address
is 021 (hex) (the second pixel in the third word) The desti-
nation block starting address is 204 (hex) (the fifth pixel in
the 33rd word) The block width is 13 (hex) and the height is
06 (hex) (corresponding to 6 scan lines) The shift value is 3
TL EE 11267 – 7