NS32FX164AV-25 National Semiconductor, NS32FX164AV-25 Datasheet - Page 20

• Manufacturer Part Number: NS32FX164AV-25
• Description: IC IMAGING COMM SGNL PROC PLCC68
• Manufacturer: National Semiconductor

Specifications of NS32FX164AV-25

• Processor Type: Advanced Imaging/Communications Signal Processor SIAP™
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NS32FX164AV-25; Q1284286

2 0 Architectural Description
2 5 GRAPHICS SUPPORT
The following sections provide a brief description of the
NS32FX164 graphics support capabilities Basic discus-
sions on frame buffer addressing and BITBLT operations
are also provided
NS32FX164 graphics support instructions can be found in
the NS32CG16 Printer Display Processor Programmer’s
Reference
2 5 1 Frame Buffer Addressing
There are two basic addressing schemes for referencing
pixels within the frame buffer Linear and Cartesian (or x-y)
Linear addressing associates a single number to each pixel
representing the physical address of the corresponding bit
in memory Cartesian addressing associates two numbers
to each pixel representing the x and y coordinates of the
pixel relative to a point in the Cartesian space taken as the
origin The Cartesian space is generally defined as having
the origin in the upper left A movement to the right increas-
es the x coordinate a movement downward increases the y
coordinate
The correspondence between the location of a pixel in the
Cartesian space and the physical (BIT) address in memory
is shown in Figure 2-20 The origin of the Cartesian space
(x
menting the x coordinate increments the bit address by one
Incrementing the y coordinate increments the bit address by
an amount representing the warp (or pitch) of the Cartesian
space Thus the linear address of a pixel at location (x y) in
the Cartesian space can be found by the following expres-
sion
Warp is the distance (in bits) in the physical memory space
between two vertically adjacent bits in the Cartesian space
Example 1 below shows two NS32FX164 instruction se-
quences to set a single pixel given the x and y coordinates
Example 2 shows how to create a fat pixel by setting four
adjacent bits in the Cartesian space
Example 1 Set pixel at location (x y)
Instruction Sequence 1
Instruction Sequence 2
MULD
ADDD
SBITD
INDEXD R1
SBITD
e
0 y
Setup R0 x coordinate
e
0) corresponds to the bit address ‘ORG’ Incre-
WARP
R0
R1
R1
R1 y coordinate
ADDR
R1
ORG
(WARP-1)
ORG
R1
e
More detailed information on the
ORG
a
R0
y WARP
Y*WARP
SET PIXEL
Y*WARP
SET PIXEL
X
a
x
BIT OFFSET
(Continued)
X
20
Example 2 Create fat pixel by setting bits at locations
Instruction Sequence
INDEXD
SBITD
ADDQD
SBITD
ADDD
SBITD
ADDQD
SBITD
2 5 2 BITBLT Fundamentals
BITBLT BIT-aligned BLock Transfer is a general operator
that provides a mechanism to move an arbitrary size rectan-
gle of an image from one part of the frame buffer to another
During the data transfer process a bitwise logical operation
can be performed between the source and the destination
data BITBLT is also called RasterOp operations on rasters
It defines two rectangular areas source and destination
and performs a logical operation (e g AND OR XOR) be-
tween these two areas and stores the result back to the
destination It can be expressed in simple notation as
Setup R0 x coordinate
FIGURE 2-20 Correspondence between
Source op Destination
R1
41
1
R1
(WARP-1)
R1
1
R1
Linear and Cartesian Addressing
(x y) (x
R1 y coordinate
R1
R1
(WARP-1)
ORG
ORG
ORG
ORG
op AND OR XOR etc
a
1 y) (x y
R1
R0
a
1) and (x
BIT ADDRESS
SET FIRST PIXEL
(X 1
SECOND PIXEL
(X
THIRD PIXEL
(X 1
LAST PIXEL
Destination
Y 1)
a
Y)
Y 1)
1 y
TL EE 11267 – 6
a
1)