NS32FX164AV-25 National Semiconductor, NS32FX164AV-25 Datasheet - Page 26

• Manufacturer Part Number: NS32FX164AV-25
• Description: IC IMAGING COMM SGNL PROC PLCC68
• Manufacturer: National Semiconductor

Specifications of NS32FX164AV-25

• Processor Type: Advanced Imaging/Communications Signal Processor SIAP™
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NS32FX164AV-25; Q1284286

2 0 Architectural Description
2 5 3 3 1 Magnifying Compressed Data
Restoring data is just one application of the SBITS and
SBITPS instructions Multiplying the ‘‘length’’ operand used
by the SBITS and SBITPS instructions causes the resulting
pattern to be wider or a multiple of ‘‘length’’
As the pattern of data is expanded it can be magnified by
2x 3x 4x
the same style of character or changes the size of a logo A
magnify in both dimensions X and Y can be accomplished
by drawing a single line then using the MOVS (Move String)
or the BB instructions to duplicate the line maintaining an
equal aspect ratio
More information on this subject is provided in the
NS32CG16 Printer Display Processor Programmer’s Refer-
ence Supplement
3 0 Functional Description
This chapter provides details on the functional characteris-
tics of the NS32FX164 microprocessor
The chapter is divided into five main sections
Instruction Execution Exception Processing Debugging
DSP Module and System Interface
3 1 INSTRUCTION EXECUTION
To execute an instruction the NS32FX164 performs the fol-
lowing operations
Under most circumstances the CPU can be conceived to
execute instructions by completing the operations above in
strict sequence for one instruction and then beginning the
sequence of operations for the next instruction However
due to the internal instruction pipelining as well as the oc-
currence of exceptions the sequence of operations per-
formed during the execution of an instruction may be al-
tered Furthermore exceptions also break the sequentiality
of the instructions executed by the CPU
Note 1 In this and following sections memory locations read by the CPU to
3 1 1 Operating States
The CPU has four operating states regarding the execution
of instructions and the processing of exceptions Reset Ex-
ecuting Instructions Processing An Exception and Waiting-
For-An-Interrupt The various states and transitions be-
tween them are shown in Figure 3-1
Whenever the RSTI signal is asserted the CPU enters the
reset state The CPU remains in the reset state until the
RSTI signal is driven inactive at which time it enters the
Executing-Instructions state In the Reset state the contents
of certain registers are initialized Refer to Section 3 5 4 for
details
Fetch the Instruction
Read Source Operands if Any (1)
Calculate Results
Write Result Operands if Any
Modify Flags if Necessary
Update the Program Counter
calculate effective addresses for Memory-Relative and External ad-
dressing modes are considered like source operands even if the
effective address is being calculated for an operand with access
class of write
10x and so on This creates several sizes of
(Continued)
26
In the Executing-Instructions state the CPU executes in-
structions It will exit this state when an exception is recog-
nized or a WAIT instruction is encountered At which time it
enters the Processing-An-Exception state or the Waiting-
For-An-Interrupt state respectively
While in the Processing-An-Exception state the CPU saves
the PC PSR and MOD register contents on the stack and
reads the new PC and module linkage information to begin
execution of the exception service procedure
Following the completion of all data references required to
process an exception the CPU enters the Executing-In-
structions state
In the Waiting-For-An-Interrupt state the CPU is idle A spe-
cial status identifying this state is presented on the system
interface (Section 3 5) When an interrupt is detected the
CPU enters the Processing-An-Exception State
3 1 2 Instruction Endings
The NS32FX164 checks for exceptions at various points
while executing instructions Certain exceptions like inter-
rupts are in most cases recognized between instructions
Other exceptions like Divide-By-Zero Trap are recognized
during execution of an instruction When an exception is
recognized during execution of an instruction the instruction
ends in one of four possible ways completed suspended
terminated or partially completed Each type of exception
causes a particular ending as specified in Section 3 2
FIGURE 3-1 Operating States
TL EE 11267 – 11