NS32FX164AV-25 National Semiconductor, NS32FX164AV-25 Datasheet - Page 43

• Manufacturer Part Number: NS32FX164AV-25
• Description: IC IMAGING COMM SGNL PROC PLCC68
• Manufacturer: National Semiconductor

Specifications of NS32FX164AV-25

• Processor Type: Advanced Imaging/Communications Signal Processor SIAP™
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NS32FX164AV-25; Q1284286

3 0 Functional Description
memory areas for any purpose exactly as they would ac-
cess external off-chip memory locations However when
the DSPM command list execution unit is active any at-
tempt to read or write a location within the above memory
areas except for accessing the CLSTAT EXT DSPMASK
DSPINT NMISTAT or ABORT control registers (see be-
low) will be treated as follows All read data will have unpre-
dictable values and any attempt to write data will not
change the DSPM memory and registers Whenever such
an access occurs NMISTAT ERR bit is set to ‘‘1’’ an NMI
request to the core is issued and the command list execu-
tion terminates In this case as the command-list execution
terminates asyncronously the currently executed command
may be aborted The DSPM RAM and the A X Y Z and
REPEAT registers may hold temporary values created in
this aborted instruction
Some of the vector instructions executable by the DSPM
can access external off-chip memory to transfer data in or
out of the internal RAM or to reference large lookup tables
Normally external memory references initiated by the
DSPM and CPU core are interleaved by the CPU core bus-
arbitration logic As a result it is the user’s responsibility to
make sure that whenever a write operation is involved the
DSPM and CPU core should not reference the same exter-
nal memory locations since the order of these transactions
is unpredictable
Each time the DSPM needs to access the external bus it
issues an internal HOLD request to the CPU core and waits
for an internal HOLD acknowledge External HOLD requests
(when the HOLD signal is asserted) have higher priority than
DSPM HOLD requests
In order to ensure fast response for time-critical interrupt
requests the DSPM external referencing mechanism will re-
linquish the core bus for one clock cycle after each memory
transaction This allows the core to use the bus for one
memory transaction To further enhance the core speed on
critical interrupt routines the EXT HOLD control flag is pro-
vided
Whenever the core sets EXT HOLD to ‘‘1’’ the DSPM stops
its external memory references When the DSPM needs to
perform an external memory reference but is disabled it
enters a HOLD state until a value of ‘‘0’’ is written to the
EXT HOLD control register
3 4 4 2 DSPM RAM Organization
The mapping of these locations to CPU core address space
is shown below where base corresponds to the start of the
mapped area (address 0xFFFE0000)
The RAM array is not restricted to use by the DSPM but can
also be used by the core as a fast zero wait-state on-chip
memory for instructions and data storage The core can ac-
cess each byte word or double-word of the RAM with no
restrictions on alignment
15
base
base
base
a
2 n
a
a
1
3
a
1
8
7
base
base
base
a
a
a
2 n
0
2
0
(RAM Location 0)
(RAM Location 1)
(RAM Location n )
(Continued)
43
3 4 5 DSPM Instruction Set
3 4 5 1 Conventions
The formal description below of DSPM command-list in-
structions is based on the ‘‘C’’ programming language us-
ing the following conventions
low
high
LENG
A
aligned addr An even number in the range 0 2
mem k
ext mem k
X
Y
Z
X n
Y n
Z n
3 4 5 2 Type Casting
The following data type definitions are used in DSPM in-
struction description
integer
aligned integer An aligned integer value as described in
real
X n
Y n
Z n
n
n
n
Bits 0 through 15 of a 32 bits entity
Bits 16 through 31 of a 32 bits entity
Value of PARAM LENGTH
Accumulator
for specifying a double word-aligned address
in internal memory
A value in internal memory whose first word
address is k where 0
A value in external memory whose first byte
address is k where 0
Vector in internal memory whose first ad-
dress is pointed to by X ADDR
Vector in internal memory whose first ad-
dress is pointed to by Y ADDR
Vector in internal memory whose first ad-
dress is pointed to by Z ADDR
A value in internal memory whose address is
formed by adding an offset to a cyclic buffer
base address The base address is formed
by clearing the (X WRAP
cant bits of X ADDR The offset within the
buffer
A value in internal memory whose address is
formed by adding an offset to a cyclic buffer
base address The base address is formed
by clearing the (Y WRAP
cant bits of Y ADDR The offset within the
buffer
A value in internal memory whose address is
formed by adding an offset to a cyclic buffer
base address The base address is formed
by clearing the (Z WRAP
cant bits of Z ADDR The offset within the
buffer
The word address of X n
The word address of Y n
The word address of Z n
c
c
c
An integer value as described in Section
3 4 2 1
Section 3 4 2 2
A real value as described in Section
3 4 2 3
2
2
2
X INCR
Y INCR
Z INCR
is
is
is
) modulo 2
) modulo 2
calculated
calculated
) modulo 2
calculated
s
s
X WRAP
Y WRAP
Z WRAP
k
k
by
by
by
k
k
b
b
b
2
2
1) less-signifi-
1) less-signifi-
1) less-signifi-
(X ADDR
(Y ADDR
16
32
(Z ADDR
16
used
a
a
a