NS32FX164AV-25 National Semiconductor, NS32FX164AV-25 Datasheet - Page 23

• Manufacturer Part Number: NS32FX164AV-25
• Description: IC IMAGING COMM SGNL PROC PLCC68
• Manufacturer: National Semiconductor

Specifications of NS32FX164AV-25

• Processor Type: Advanced Imaging/Communications Signal Processor SIAP™
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NS32FX164AV-25; Q1284286

Figure 2-22(b) demonstrates a case in which the horizontal
2 0 Architectural Description
curs any time the screen is moved in a purely vertical direc-
tion as in scrolling text It should be noted that in both of
these cases the choice of horizontal BITBLT direction may
be made arbitrarily
BITBLT direction may not be chosen arbitrarily This is an
instance of purely horizontal movement of data (panning)
Because the movement from source to destination involves
data within the same scan line the incorrect direction of
movement will overwrite data which will be needed later In
this example the correct direction is from right to left
2 5 2 5 BITBLT Variations
The ‘‘classical’’ definition of BITBLT as described in
‘‘Smalltalk-80 The Language and its Implementation’’ by
Adele Goldberg and David Robson provides for three oper-
ands source destination and mask texture This third oper-
and is commonly used in monochrome systems to incorpo-
rate a stipple pattern into an area These stipple patterns
provide the appearance of multiple shades of gray in single-
bit-per-pixel systems in a manner similar to the ‘‘halftone’’
process used in printing
While the NS32FX164 and the external BPU (if used) are
essentially two-operand devices three-operand BITBLT op-
erations can be implemented quite flexibly and efficiently by
performing the two operations serially
2 5 3 GRAPHICS SUPPORT INSTRUCTIONS
The NS32FX164 provides eleven instructions for supporting
graphics oriented applications These instructions are divid-
ed into three groups according to the operations they per-
form General descriptions for each of them and the related
formats are provided in the following sections
2 5 3 1 BITBLT (BIT-aligned BLock Transfer)
This group includes seven instructions They are used to
move characters and objects into the frame buffer which will
be printed or displayed One of the instructions works in
conjunction with an external BITBLT Processing Unit (BPU)
to maximize performance The other six are executed by the
NS32FX164
BIT-aligned BLock Transfer
Syntax BB(function) Options
Setup
Function
Options
Texture op1 Source op2 Destination
R0
R1
R2
R3
R4
R5
R6
R7
0(SP)
AND OR XOR FOR STOD
IA
DA
S
b
S
base address source data
base address destination data
shift value
height (in lines)
first mask
second mask
source warp (adjusted)
destination warp (adjusted)
width (in words)
Increasing Address (default option)
When IA is selected scan lines are
transferred in the increasing BIT BYTE
order
Decreasing Address
True Source (default option)
Inverted Source
Destination
(Continued)
23
These five instructions perform standard BITBLT operations
between source and destination blocks The operations
available include the following
BBAND
BBOR
BBXOR
BBFOR
BBSTOD
‘src’ and ‘
Source’ respectively ‘dst’ stands for ‘Destination’
Note 1 For speed reasons the BB instructions require the masks to be
Note 2 The options
Note 3 BBFOR performs the same operation as BBOR with IA and S op-
Note 4 IA and DA are mutually exclusive and so are S and
Note 5 The width is defined as the number of words of source data to read
Note 6 An odd number of bytes can be specified for the source warp
The horizontal and vertical directions of the BITBLT opera-
tions performed by the above instructions with the excep-
tion of BBFOR are both programmable The horizontal di-
rection is controlled by the IA and DA options The vertical
direction is controlled by the sign of the source and destina-
tion warps Figure 2-23 and Table 2-3 show the format of
the BB instructions and the encodings for the ‘op’ and ‘i’
fields
BIT-aligned Word Transfer
Syntax BITWT
Setup
The BITWT instruction performs a fast logical OR operation
between a source word and a destination double word
stores the result into the destination double word and incre-
ments registers R0 and R1 by two Before performing the
OR operation the source word is shifted left (i e in the
direction of increasing bit numbers) by the value in register
R2
23
0 0 0 0 0 0 D X S 0
D is set when the DA option is selected
S is set when the
X is set for BBAND and it is clear for all other BB instructions
Instruction
BBAND
BBOR
BBXOR
BBFOR
BBSTOD
specified with respect to the source block In Figure 2-21 masking
was defined relative to the destination block
tion
tions
However word alignment of source scan lines will result in faster
execution
TABLE 2-3 ‘op’ and ‘i’ Field Encodings
FIGURE 2-23 BB Instructions Format
R0
R1
R2
b
src’ stand for ‘True Source’ and ‘Inverted
b
b
b
b
src
src
src
src
src
src
src
src
src
16 15
b
b
S option is selected
Base address source word
Base address destination double word
Shift value
S and DA are not available for the BBFOR instruc-
Options
Yes
Yes
Yes
Yes
No
AND
AND
OR
OR
XOR
XOR
OR
TO
TO
op
dst
dst
dst
dst
dst
dst
dst
dst
dst
‘op’ Field
i
1010
0110
1110
1100
0100
8 7
0 0 0 0 1 1 1 0
b
‘i’ Field
S
11
01
01
01
01
0