NS32FX164AV-25 National Semiconductor, NS32FX164AV-25 Datasheet - Page 64

• Manufacturer Part Number: NS32FX164AV-25
• Description: IC IMAGING COMM SGNL PROC PLCC68
• Manufacturer: National Semiconductor

Specifications of NS32FX164AV-25

• Processor Type: Advanced Imaging/Communications Signal Processor SIAP™
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NS32FX164AV-25; Q1284286

3 0 Functional Description
3 5 5 5 Interrupt Control Cycles
Activating the INT or NMI pin on the CPU will initiate one or
more bus cycles whose purpose in interrupt control rather
than the tranfer of instructions or data Execution of the
Return from Interrupt Instruction (RETI) will also cause In-
terrupt Control bus cycles These differ from instruction or
If the address is Odd (A0 is high) then the CPU applies HBE low and reads the vector number from bits 8–15 of the Data Bus The vector number may be in the
range 0–225
If the Cascaded ICU Address is Even (A0 is low) then the CPU applies HBE high and reads the vector number from bits 0–7 of the Data Bus
Interrupt Acknowledge
Cycle
Interrupt Return
None Performed through Return from Trap (RETT) instruction
Interrupt Acknowledge
Interrupt Return
None Performed through Return from Trap (RETT) instruction
Interrupt Acknowledge
Interrupt Return
Interrupt Acknowledge
(The CPU here uses the Cascade Index to find the Cascade Address )
Interrupt Return
(The CPU here uses the Cascade Index to find the Cascade Address )
1
1
1
1
1
2
1
2
Status
0100
0100
0100
0110
0100
0101
0110
0111
FFFE00
FFFE00
FFFE00
FFFE00
FFFE00
FFFF00
Address
Cascade
Cascade
Address
Address
16
16
16
16
16
16
C Vectored Interrupt Sequence Non-Cascaded
A Non-Maskable Interrupt Control Sequence
B Non-Vectored Interrupt Control Sequence
D Vectored Interrupt Sequence Cascaded
(Continued)
TABLE 3-4 Interrupt Sequences
DDIN
0
0
0
0
0
0
0
0
HBE
1 or
1 or
0
0
1
1
1
1
1
1
64
data transfers only in the status presented on pins ST0–
ST3 All Interrupt Control cycles are single-byte Read cy-
cles
Table 3-4 shows the Interrupt Control sequences associat-
ed with each interrupt and with the return from its service
routine For full details of the NS32FX164 interrupt struc-
ture see Section 3 2
0 or
0 or
A0
1
1
0
0
0
0
0
0
Vector range 0– 255 on appropriate
half or Data Bus for even odd
address
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
High Bus
Vector
Range 0 – 127
Vector Same as
in Previous Int
Ack Cycle
Cascade Index
range
Cascade Index
same as in
previous Int
Ack Cycle
Don’t Care
Don’t Care
Don’t Care
b
Low Bus
16 to
b
1