NS32FX164AV-25 National Semiconductor, NS32FX164AV-25 Datasheet - Page 27

• Manufacturer Part Number: NS32FX164AV-25
• Description: IC IMAGING COMM SGNL PROC PLCC68
• Manufacturer: National Semiconductor

Specifications of NS32FX164AV-25

• Processor Type: Advanced Imaging/Communications Signal Processor SIAP™
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: *NS32FX164AV-25; Q1284286

3 0 Functional Description
3 1 2 1 Completed Instructions
When an exception is recognized after an instruction is
completed the CPU has performed all of the operations for
that instruction and for all other instructions executed since
the last exception occurred Result operands have been
written flags have been modified and the PC saved on the
Interrupt Stack contains the address of the next instruction
to execute The exception service procedure can at its con-
clusion execute the RETT instruction (or the RETI instruc-
tion for maskable interrupts) and the CPU will begin execut-
ing the instruction following the completed instruction
3 1 2 2 Suspended Instructions
An instruction is suspended when one of several trap condi-
tions is detected during execution of the instruction A sus-
pended instruction has not been completed but all other
instructions executed since the last exception occurred
have been completed Result operands and flags due to be
affected by the instruction may have been modified but only
modifications that allow the instruction to be executed again
and completed can occur For certain exceptions (Trap
(UND) the CPU clears the P-flag in the PSR before saving
the copy that is pushed on the Interrupt Stack The PC
saved on the Interrupt Stack contains the address of the
suspended instruction
To complete a suspended instruction the exception service
procedure takes either of two actions
1 The service procedure can simulate the suspended in-
2 The suspended instruction can be executed again after
Note 1 It may be necessary for the exception service procedure to alter the
struction’s execution After calculating and writing the in-
struction’s results the flags in the PSR copy saved on the
Interrupt Stack should be modified and the PC saved on
the Interrupt Stack should be updated to point to the next
instruction to execute The service procedure can then
execute the RETT instruction and the CPU begins exe-
cuting the instruction following the suspended instruction
This is the action taken when floating-point instructions
are simulated by software in systems without a hardware
floating-point unit
the service procedure has eliminated the trap condition
that caused the instruction to be suspended The service
procedure should execute the RETT instruction at its con-
clusion then the CPU begins executing the suspended
instruction again This is the action taken by a debugger
when it encounters a BPT instruction that was temporarily
placed in another instruction’s location in order to set a
breakpoint
P-flag in the PSR copy saved on the Interrupt Stack If the exception
service procedure simulates the suspended instruction and the P-
flag was cleared by the CPU before saving the PSR copy then the
saved T-flag must be copied to the saved P-flag (like the floating-
point instruction simulation described above) Or if the exception
service procedure executes the suspended instruction again and
the P-flag was not cleared by the CPU before saving the PSR copy
then the saved P-flag must be cleared (like the breakpoint trap de-
scribed above) Otherwise no alteration to the saved P-flag is nec-
essary
(Continued)
27
3 1 2 3 Terminated Instructions
An instruction being executed is terminated when reset oc-
curs Any result operands and flags due to be affected by
the instruction are undefined as is the contents of the PC
3 1 2 4 Partially Completed Instructions
When an interrupt condition is recognized during execution
of a string instruction the instruction is said to be partially
completed A partially completed instruction has not com-
pleted but all other instructions executed since the last ex-
ception occurred have been completed Result operands
and flags due to be affected by the instruction may have
been modified but the values stored in the string pointers
and other general-purpose registers used during the instruc-
tion’s execution allow the instruction to be executed again
and completed
The CPU clears the P-flag in the PSR before saving the
copy that is pushed on the Interrupt Stack The PC saved on
the Interrupt Stack contains the address of the partially
completed instruction The exception service procedure
can at its conclusion simply execute the RETT instruction
(or the RETI instruction for maskable interrupts) and the
CPU will resume executing the partially completed instruc-
tion
3 1 3 Slave Processor Instructions
The NS32FX164 supports only one group of instructions
the floating-point instruction set as being executable by a
slave processor The floating-point instruction set is validat-
ed by the F-bit in the CFG register
If a floating-point instruction is encountered and the F-bit in
the CFG register is not set a Trap (UND) will result without
any slave processor communication attempted by the CPU
This allows software emulation in case an external floating-
point unit (FPU) is not used
3 1 3 1 Slave Processor Protocol
Slave Processor instructions have a three-byte Basic In-
struction field consisting of an ID Byte followed by an Oper-
ation Word The ID Byte has three functions
1 It identifies the instruction as being a Slave Processor
2 It specifies which Slave Processor will execute it
3 It determines the format of the following Operation Word
Upon receiving a Slave Processor instruction the CPU initi-
ates the sequence outlined in Figure 3-2 While applying
Status Code 1111 (Broadcast ID Section 3 5 5 1) the CPU
transfers the ID Byte on the least-significant half of the Data
Bus (AD0– AD7) All Slave Processors input this byte and
decode it The Slave Processor selected by the ID Byte is
activated and from this point the CPU is communicating
only with it If any other slave protocol was in progress (e g
an aborted Slave instruction) this transfer cancels it
instruction
of the instruction