ATmega1284PR231

Manufacturer Part NumberATmega1284PR231
ManufacturerAtmel Corporation
ATmega1284PR231 datasheets
 

Specifications of ATmega1284PR231

Flash (kbytes)128 KbytesMax. Operating Frequency20 MHz
Max I/o Pins32Spi3
Twi (i2c)1Uart2
Adc Channels8Adc Resolution (bits)10
Adc Speed (ksps)15Analog Comparators1
Crypto EngineAESSram (kbytes)16
Eeprom (bytes)4096Operating Voltage (vcc)1.8 to 3.6
Timers3Frequency Band2.4 GHz
Max Data Rate (mb/s)2Antenna DiversityYes
External Pa ControlYesPower Output (dbm)3
Receiver Sensitivity (dbm)-101Receive Current Consumption (ma)13.2
Transmit Current Consumption (ma)14.4Link Budget (dbm)104
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Features
High Performance RF-CMOS 2.4 GHz Radio Transceiver Targeted for IEEE 802.15.4
®
ZigBee
, 6LoWPAN, RF4CE, SP100, WirelessHART
Industry Leading Link Budget (104 dB)
– Receiver Sensitivity -101 dBm
– Programmable Output Power from -17 dBm up to +3 dBm
Ultra-Low Current Consumption:
SLEEP
0.02 µA
=
TRX_OFF
=
0.4 mA
RX_ON
12.3 mA
=
BUSY_TX
14 mA (at max. Transmit Power of +3 dBm)
=
Ultra-Low Supply Voltage (1.8V to 3.6V) with Internal Regulator
Optimized for Low BoM Cost and Ease of Production:
– Few External Components Necessary (Crystal, Capacitors and Antenna)
– Excellent ESD Robustness
Easy to Use Interface:
– Registers, Frame Buffer and AES Accessible through Fast SPI
– Only Two Microcontroller GPIO Lines Necessary
– One Interrupt Pin from Radio Transceiver
– Clock Output with Prescaler from Radio Transceiver
Radio Transceiver Features:
– 128-byte FIFO (SRAM) for Data Buffering
– Programmable Clock Output, to Clock the Host Microcontroller or as Timer
Reference
– Integrated RX/TX Switch
– Fully Integrated, Fast Settling PLL to support Frequency Hopping
– Battery Monitor
– Fast Wake-Up Time < 0.4 msec
Special IEEE 802.15.4-2006 Hardware Support:
– FCS Computation and Clear Channel Assessment
– RSSI Measurement, Energy Detection and Link Quality Indication
MAC Hardware Accelerator:
– Automated Acknowledgement, CSMA-CA and Retransmission
– Automatic Address Filtering
– Automated FCS Check
Extended Feature Set Hardware Support:
– AES 128-bit Hardware Accelerator
– RX/TX Indication (external RF Front-End Control)
– RX Antenna Diversity
– Supported PSDU data rates: 250 kb/s, 500 kb/s, 1 Mb/s and 2 Mb/s
– True Random Number Generation for Security Application
Industrial and Extended Temperature Range:
– -40°C to +85°C and -40°C to +125°C
I/O and Packages:
– 32-pin Low-Profile QFN Package 5 x 5 x 0.9 mm³
– RoHS/Fully Green
Compliant to IEEE 802.15.4-2006 and IEEE 802.15.4-2003
Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-T66, RSS-210
,
and ISM Applications
Low Power
2.4 GHz
Transceiver for
ZigBee,
IEEE 802.15.4,
6LoWPAN,
RF4CE, SP100,
WirelessHART,
and ISM
Applications
AT86RF231-ZU
AT86RF231-ZF
8111C–MCU Wireless–09/09

ATmega1284PR231 Summary of contents

  • Page 1

    Features • High Performance RF-CMOS 2.4 GHz Radio Transceiver Targeted for IEEE 802.15.4 ® ZigBee , 6LoWPAN, RF4CE, SP100, WirelessHART • Industry Leading Link Budget (104 dB) – Receiver Sensitivity -101 dBm – Programmable Output Power from -17 dBm up ...

  • Page 2

    Pin-out Diagram Figure 1-1. Note: 8111C–MCU Wireless–09/09 AT86RF231 Pin-out Diagram ...

  • Page 3

    Pin Descriptions Table 1-1. Pin Description AT86RF231 Pins Name Type 1 DIG3 Digital output (Ground) 2 DIG4 Digital output (Ground) 3 AVSS Ground 4 RFP RF I/O 5 RFN RF I/O 6 AVSS Ground 7 DVSS Ground 8 /RST ...

  • Page 4

    Table 1-1. Pin Description AT86RF231 (Continued) Pins Name Type 29 AVDD Supply 30 AVSS Ground 31 AVSS Ground 32 AVSS Ground Paddle AVSS Ground 8111C–MCU Wireless–09/09 Description Regulated 1.8V voltage regulator; analog domain, see Analog ground Analog ground Analog ground ...

  • Page 5

    Analog and RF Pins 1.2.1 Supply and Ground Pins EVDD, DEVDD EVDD and DEVDD are analog and digital supply voltage pins of the AT86RF231 radio transceiver. AVDD, DVDD AVDD and DVDD are outputs of the internal 1.8V voltage regulators. ...

  • Page 6

    The RF port DC values depend on the operating state, refer to page 33. In TRX_OFF state, when the analog front-end is disabled (see “TRX_OFF - Clock State” on page voltage. In transmit mode, a control loop provides a common-mode ...

  • Page 7

    Digital Pins The AT86RF231 provides a digital microcontroller interface. The interface comprises a slave SPI (/SEL, SCLK, MOSI and MISO) and additional control signals (CLKM, IRQ, SLP_TR, /RST and DIG2). The microcontroller interface is described in detail in Interface” ...

  • Page 8

    Register Description Register 0x03 (TRX_CTRL_0): The TRX_CTRL_0 register controls the drive current of the digital output pads and the CLKM clock rate. Bit 7 6 0x03 PAD_IO Read/Write R/W R/W Initial Value 0 0 • Bit [7:6] - PAD_IO ...

  • Page 9

    Disclaimer Typical values contained in this datasheet are based on simulations and testing. Min and Max values are available when the radio transceiver has been fully characterized. 3. Overview The AT86RF231 is a feature rich, low-power 2.4 GHz radio ...

  • Page 10

    General Circuit Description This single-chip radio transceiver provides a complete radio transceiver interface between an antenna and a microcontroller. It comprises the analog radio, digital modulation and demodula- tion including time and frequency synchronization and data buffering. The number ...

  • Page 11

    An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to be transmitted or the received data. The configuration of the AT86RF231, reading and writing of Frame Buffer is controlled by the SPI interface and additional control ...

  • Page 12

    Application Circuits 5.1 Basic Application Schematic A basic application schematic of the AT86RF231 with a single-ended RF connector is shown in Figure 5-1 on page RF port impedance using balun B1. The capacitors C1 and C2 provide AC coupling ...

  • Page 13

    I/O signals. This is especially required for the High Data Rate Modes, refer to Crosstalk from digital signals on the crystal pins or the RF pins can degrade the ...

  • Page 14

    Extended Feature Set Application Schematic The AT86RF231 supports additional features like: • • • • • An extended feature set application schematic illustrating the use of the AT86RF231 Extended Feature Set, see ure 5-2 on page is possible to ...

  • Page 15

    DIG1/DIG2, the RF signal is amplified by an optional low-noise amplifier (N2) and fed to the radio transceiver using the second RX/TX switch (SW1). During transmit the AT86RF231 TX signal is amplified using an external PA (N1) and ...

  • Page 16

    Microcontroller Interface This section describes the AT86RF231 to microcontroller interface. The interface comprises a slave SPI and additional control signals; see are described below. Figure 6-1. Microcontrollers with a master SPI such as Atmel's AVR family interface directly to ...

  • Page 17

    Table 6-1. SLP_TR /RST DIG2 6.1 SPI Timing Description Pin 17 (CLKM) can be used as a microcontroller master clock source. If the microcontroller derives the SPI master clock (SCLK) directly from CLKM, the SPI operates in synchronous mode, otherwise ...

  • Page 18

    The SPI is based on a byte-oriented protocol and is always a bidirectional communication between master and slave. The SPI master starts the transfer by asserting /SEL = L. Then the master generates eight SPI clock cycles to transfer one ...

  • Page 19

    SPI Protocol Each SPI sequence starts with transferring a command byte from the SPI master via MOSI (see Table 6-2 on page additional mode-dependent information. Table 6-2. SPI Command Byte definition Bit 7 Bit 6 Bit 5 Bit 4 ...

  • Page 20

    Figure 6-5. Each register access must be terminated by setting /SEL = H. Figure 6-6 on page 20 and read respectively. Figure 6-6. Example SPI Sequence - Register Access Mode Register Write Access /SEL SCLK MOSI WRITE COMMAND MISO PHY_STATUS ...

  • Page 21

    Note, the Frame Buffer read access can be terminated at any time without any consequences by setting /SEL = H, e.g. after reading the PHR byte only. On Frame Buffer write access the second byte transferred on MOSI contains the ...

  • Page 22

    Figure 6-10. Example SPI Sequence - Frame Buffer Write of a Frame with 4 byte PSDU /SEL SCLK MOSI COMMAND MISO PHY_STATUS Access violations during a Frame Buffer read or write access are indicated by interrupt IRQ_6 (TRX_UR). For further ...

  • Page 23

    On SRAM write access, one or more bytes of write data are transferred on MOSI starting with the third byte of the access sequence (see On SRAM read or write accesses do not attempt to read or write bytes beyond ...

  • Page 24

    Radio Transceiver Status information Each SPI access can be configured to return status information of the radio transceiver (PHY_STATUS) to the microcontroller using the first byte of the data transferred via MISO. The content of the radio transceiver status ...

  • Page 25

    Radio Transceiver Identification The AT86RF231 can be identified by four registers. One register contains a unique part number and one register the corresponding version number. Two additional registers contain the JEDEC manufacture ID. 6.4.1 Register Description - AT86RF231 Identification ...

  • Page 26

    Table 6-6. Register Bit MAN_ID_0 Register 0x1F (MAN_ID_1): Bit +0x1F Read/Write Reset Value • Bit [7:0] - MAN_ID_1 Bits [15:8] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_1. Bits [7:0] are stored in register 0x1E (MAN_ID_0). ...

  • Page 27

    Sleep/Wake-up and Transmit Signal (SLP_TR) Pin 11 (SLP_TR multi-functional pin. Its function relates to the current state of the AT86RF231 and is summarized in explained in detail Table 6-8. SLP_TR Multi-functional Pin Transceiver Status Function PLL_ON TX ...

  • Page 28

    Figure 6-15. Sleep and Wake-up Initiated by Asynchronous Microcontroller Timer SLP_TR CLKM 35 CLKM clock cycles Note: Timing figure t RX_ON and RX_AACK_ON states For synchronous systems, where CLKM is used as a microcontroller clock source and the SPI master ...

  • Page 29

    Interrupt Logic 6.6.1 Overview The AT86RF231 differentiates between nine interrupt events (eight physical interrupt registers, one shared by two functions). Each interrupt is enabled by setting the corresponding bit in the interrupt mask register 0x0E (IRQ_MASK). Internally, each pending ...

  • Page 30

    Note that AWAKE_END interrupt can usually not be seen when the transceiver enters TRX_OFF state after RESET, because register 0x0E (IRQ_MASK) is reset to mask all inter- rupts. In this case, state TRX_OFF is normally entered before the microcontroller could ...

  • Page 31

    Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit 7 6 +0x04 PA_EXT_EN IRQ_2_EXT_EN Read/Write R/W R/W Reset Value 0 0 • Bit 7 - PA_EXT_EN ...

  • Page 32

    Bit 0 - IRQ_POLARITY The default polarity of the IRQ pin is active high. The polarity can be configured to active low via register bit IRQ_POLARITY, see Table 6-11. Register Bit IRQ_POLARITY This setting does not affect the polarity ...

  • Page 33

    Operating Modes 7.1 Basic Operating Mode This section summarizes all states to provide the basic functionality of the AT86RF231, such as receiving and transmitting frames, the power up sequence and sleep. The Basic Operating Mode is designed for IEEE ...

  • Page 34

    A successful state change can be verified by reading the radio transceiver status from register 0x01 (TRX_STATUS). If TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS) the AT86RF231 state transition. Do not try to initiate a further state ...

  • Page 35

    All digital inputs are pulled-up or pulled-down during P_ON state, refer to and Pull-Down Configuration” on page GPIO signals are floating after power on or reset. The input pull-up and pull-down circuitry is dis- abled when the radio transceiver leaves ...

  • Page 36

    Entering the TRX_OFF state from P_ON, SLEEP, or RESET state is indicated by interrupt IRQ_4 (AWAKE_END). 7.1.2.4 PLL_ON - PLL State Entering the PLL_ON state from TRX_OFF state enables the analog voltage regulator (AVREG) first. After the voltage regulator has ...

  • Page 37

    This state can only be entered by setting pin 11 (SLP_TR while the radio transceiver is in the RX_ON state, refer to State” on page SLP_TR pin, see down sequence. Note that for CLKM clock rates 250 kHz ...

  • Page 38

    A reset forces the radio transceiver into TRX_OFF state. If the device is still in the P_ON state it remains in the P_ON state though. A reset is initiated with pin /RST = L and the state is left after ...

  • Page 39

    Figure 7-2. Timing of RX_START, AMI and TRX_END Interrupts in Basic Operating Mode -16 0 TRX_STATE PLL_ON SLP_TR IRQ Typ. Processing Delay 16 µs Number of Octets Frame Content TRX_STATE IRQ Interrupt latency 7.1.4 Basic Operating Mode Timing The following ...

  • Page 40

    Wake-up Procedure The wake-up procedure from SLEEP state is shown in Figure 7-4. Event State Block Time The radio transceivers SLEEP state is left by releasing pin SLP_TR to logic low. This restarts the XOSC and DVREG. After t ...

  • Page 41

    BUSY_TX and RX_ON States The transition from PLL_ON to BUSY_TX state and subsequent to RX_ON state is shown in Figure 7-6 on page Figure 7-6. Pin State Block Command Time Starting from PLL_ON state it is further assumed that ...

  • Page 42

    L sets all registers to their default values. Exceptions are register bits CLKM_CTRL (reg- ister 0x03, TRX_CTRL_0), refer to 117. After releasing the reset pin (/RST = H) the wake-up sequence including an FTN calibration cycle is performed, ...

  • Page 43

    Table 7-1. State Transition Timing (Continued) No Symbol Transition ⇒ PLL_ON TR10 ⇒ BUSY_TX TR11 ⇒ All states TR12 ⇒ RESET TR13 Various ⇒ TR14 states The state transition timing ...

  • Page 44

    Register Description Register 0x01 (TRX_STATUS): A read access to TRX_STATUS register signals the current radio transceiver state. A state change is initiated by writing a state transition command to register bits TRX_CMD (register 0x02, TRX_STATE). Alternatively a state transition ...

  • Page 45

    Table 7-3. Register Bits TRX_STATUS Notes: 8111C–MCU Wireless–09/09 Radio Transceiver Status, Register Bits TRX_STATUS Value State Description 0x00 P_ON 0x01 BUSY_RX 0x02 BUSY_TX 0x06 RX_ON 0x08 TRX_OFF (CLK Mode) 0x09 PLL_ON (TX_ON) (3) 0x0F SLEEP (1) 0x11 BUSY_RX_AACK (1) 0x12 ...

  • Page 46

    Register 0x02 (TRX_STATE): The radio transceiver states are controlled via register bits TRX_CMD, which receives the state transition commands. This register is used for Basic and Extended Operating Mode, refer to Operating Mode” on page Bit 7 6 +0x02 TRAC_STATUS ...

  • Page 47

    Extended Operating Mode The Extended Operating Mode is a hardware MAC accelerator and goes beyond the basic radio transceiver functionality provided by the Basic Operating Mode. It handles time critical MAC tasks, requested by the IEEE 802.15.4 standard, by ...

  • Page 48

    Figure 7-8. Extended Operating Mode State Diagram (Power-on after V FORCE_TRX_OFF (all modes except SLEEP) SHR Detected BUSY_RX (Receive State) Frame End RX_ON_NOCLK (Rx Listen State) CLKM=OFF SHR Detected BUSY_RX_AACK Trans- action Finished SHR Detected BUSY_RX_ AACK_NOCLK Frame CLKM=OFF Rejected ...

  • Page 49

    State Control The Extended Operating Mode states RX_AACK and TX_ARET are controlled via register bits TRX_CMD (register 0x02, TRX_STATE), which receives the state transition commands. The states are entered from TRX_OFF or PLL_ON state as illustrated by completion of ...

  • Page 50

    Configuration The use of the Extended Operating Mode is based on Basic Operating Mode functionality. Only features beyond the basic radio transceiver functionality are described in the following sections. For details on the Basic Operating Mode refer to 33. ...

  • Page 51

    The CSMA_SEED_0 and CSMA_SEED_1 register bits (registers 0x2D, 0x2E) define a random seed for the back-off-time random-number generator in the AT86RF231. The MAX_BE and MIN_BE register bits (register 0x2F) sets the maximum and minimum CSMA back-off exponent (according to [1]). ...

  • Page 52

    The status of the RX_AACK operation is indicated by register bits TRAC_STATUS (register 0x02, TRAC_STATUS), see 68. During the operations described above the AT86RF231 remains in BUSY_RX_AACK state. 8111C–MCU Wireless–09/09 Section 7.2.7 “Register Description - Control Registers” on page AT86RF231 ...

  • Page 53

    Figure 7-9. Flow Diagram of RX_AACK Note 1: Address match, Promiscuous Mode and Reserved Frames radio transceiver in Promiscuous Mode, or configured to receive Reserved Frames handles received frames passing the third level of filtering - For details ...

  • Page 54

    Description of RX_AACK Configuration Bits Overview Table 7-5 on page 54 transaction. For address filtering it is further required to setup address registers to match to the expected address. Configuration and address bits are to be set in TRX_OFF ...

  • Page 55

    OQPSK_DATA_RATE • SFD_VALUE • ANT_DIV • RX_PDT_LEVEL are completely independent from RX_AACK mode. Each of these operating modes can be com- bined with the RX_AACK mode. 7.2.3.2 Configuration of IEEE Scenarios Normal Device Table 7-6 on page 55 ating ...

  • Page 56

    The same holds for PAN coordinators, see PAN-Coordinator Table 7-7. Register Address 0x20,0x21 0x22,0x23 0x24, ........... 0x2B 0x0C 0x2C 0x2E 0x2E 0x2E Promiscuous Mode The promiscuous mode is described in IEEE 802.15.4-2006, section 7.5.6.2. This mode is fur- ...

  • Page 57

    Only second level filter rules as defined by IEEE 802.15.4-2006, section 7.5.6.2, are applied to the received frame. Table 7-8 on page 57 Table 7-8. Register Address 0x20,0x21 0x22,0x23 0x24, ... 0x2B 0x17 0x2E 0x2E If the radio transceiver is ...

  • Page 58

    Configuration of non IEEE 802.15.4 Compliant Scenarios Sniffer Table 7-9 on page 58 RX_AACK configuration bits, refer to All frames received are indicated by an IRQ_2 (RX_START) and IRQ_3 (TRX_END). After frame reception register bit RX_CRC_VALID (register 0x06, PHY_RSSI) ...

  • Page 59

    Table 7-10. 0x2E 0x2E 0x2E There are two different options for handling reserved frame types. 1. AACK_UPLD_RES_FT = 1, AACK_FLT_RES_FT = 0: Any non-corrupted frame with a reserved frame type is indicated by an IRQ_3 (TRX_END) interrupt. No further address ...

  • Page 60

    Table 7-11. Register Address 0x17 Note that this feature can be used in all scenarios, independent of other configurations. How- ever, shorter acknowledgment timing is especially useful when using High Data Rate Modes to increase battery lifetime and to improve ...

  • Page 61

    Frame Filtering Frame Filtering is an evaluation whether or not a received frame is dedicated for this node. To accept a received frame and to generate an address match interrupt IRQ_5 (AMI) a filtering pro- cedure as described in ...

  • Page 62

    RX_AACK Slotted Operation - Slotted Acknowledgement AT86RF231 supports slotted acknowledgement operation, refer to IEEE 802.15.4-2006, section 7.5.6.4.2, in conjunction with the microcontroller. In RX_AACK mode with register bit SLOTTED_OPERATION (register 0x2C, XAH_CTRL_0) set, the transmission of an acknowledgement frame ...

  • Page 63

    Figure 7-11. Example Timing of an RX_AACK Transaction 0 64 Frame Type TRX_STATE RX_AACK_ON RX/TX IRQ Typ. Processing Delay If register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) is set, an acknowledgment frame is sent already 2 symbol times after the reception ...

  • Page 64

    TX_ARET_ON - Transmit with Automatic Retry and CSMA-CA Retry Figure 7-12. Flow Diagram of TX_ARET 8111C–MCU Wireless–09/09 TRX_STATE = TX_ARET_ON frame_rctr = 0 N Start TX Y TRX_STATE = BUSY_TX_ARET TRAC_STATUS = INVALID (see Note 1) Note 1: If ...

  • Page 65

    Overview The implemented TX_ARET algorithm is shown in In TX_ARET mode, the AT86RF231 first executes the CSMA-CA algorithm, as defined by IEEE 802.15.4-2006, section 7.5.1.4, initiated by a transmit start event. If the channel is IDLE a frame is transmitted ...

  • Page 66

    Table 7-12. Value Note that if no ACK is expected (according to the content of the received frame in the Frame Buffer), the radio transceiver issues IRQ_3 (TRX_END) directly after the frame transmission has been ...

  • Page 67

    TRAC_STATUS = SUCCESS_DATA_PENDING if the frame pending subfield of the received ACK frame was set to 1. 7.2.5 Interrupt Handling The interrupt handling in the Extended Operating Mode is similar to the Basic Operating Mode, refer to setting the ...

  • Page 68

    Register Summary The following registers are to be configured to control the Extended Operating Mode: Table 7-14. Reg.-Addr 0x01 0x02 0x04 0x08 0x09 0x17 0x20 - 0x2B 0x2C 0x2D 0x2E 0x2F 7.2.7 Register Description - Control Registers Register 0x01 ...

  • Page 69

    Table 7-15. Register Bit TRX_STATUS Notes: Register 0x02 (TRX_STATE): The AT86RF231 radio transceiver states are controlled via register TRX_STATE using register bits TRX_CMD. The read-only register bits TRAC_STATUS indicate the status or result of an Extended Operating Mode transaction. A ...

  • Page 70

    Section 7.2.3 “RX_AACK_ON - Receive with Automatic ACK” on page 51 “TX_ARET_ON - Transmit with Automatic Retry and CSMA-CA Retry” on page Table 7-16. Register Bits TRAC_STATUS Notes: TX_ARET SUCCESS_DATA_PENDING: RX_AACK SUCCESS_WAIT_FOR_ACK: • Bit [4:0] - TRX_CMD A write access ...

  • Page 71

    Notes: Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit 7 6 +0x04 PA_EXT_EN IRQ_2_EXT_EN TX_AUTO_CRC_ON Read/Write R/W R/W Reset Value 0 0 • Bit 7 ...

  • Page 72

    Bit 5 - AACK_FLTR_RES_FT This register bit shall only be set if AACK_UPLD_RES_FT = 1. If AACK_FLTR_RES_FT = 1 reserved frame types are filtered similar to data frames as speci- fied in IEEE 802.15.4-2006. Reserved frame types are explained ...

  • Page 73

    Register 0x2C (XAH_CTRL_0): Register 0x2C (XAH_CTRL_0 control register for Extended Operating Mode. Bit 7 6 +0x2C MAX_FRAME_RETRIES Read/Write R/W R/W Reset Value 0 0 • Bit [7:4] - MAX_FRAME_RETRIES The setting of MAX_FRAME_RETRIES in TX_ARET mode specifies the ...

  • Page 74

    Bit [7:0] - CSMA_SEED_0 This register contains the lower 8-bit of the CSMA_SEED, bits [7:0]. The higher 3 bit are part of register bits CSMA_SEED_1 (register 0x2E, CSMA_SEED_1). CSMA_SEED is the seed for the random number generation that determines ...

  • Page 75

    AACK_SET_PD is also copied into the frame pending subfield of the acknowledgment frame for any MAC command frame with a frame version that have the security enabled subfield set to 1. This is done in the ...

  • Page 76

    Register Description - Address Registers Register 0x20 (SHORT_ADDR_0): This register contains the lower 8 bit of the MAC short address for Frame Filter address recogni- tion, bits [7:0]. Bit +0x20 Read/Write Reset Value Register 0x21 (SHORT_ADDR_1): This register contains ...

  • Page 77

    Register 0x24 (IEEE_ADDR_0): This register contains the lower 8 bit of the MAC IEEE address for Frame Filter address recogni- tion, bits [7:0]. Bit +0x24 Read/Write Reset Value Register 0x25 (IEEE_ADDR_1): This register contains 8 bit of the MAC IEEE ...

  • Page 78

    Register 0x28 (IEEE_ADDR_4): This register contains 8 bit of the MAC IEEE address for Frame Filter address recognition, bits [39:32]. Bit +0x28 Read/Write Reset Value Register 0x29 (IEEE_ADDR_5): This register contains 8 bit of the MAC IEEE address for Frame ...

  • Page 79

    Functional Description 8.1 Introduction - IEEE 802.15.4 - 2006 Frame Format Figure 8-1 on page 79 defined by IEEE 802.15.4. access control (MAC) layer. Figure 8-1. IEEE 802.15.4 Frame Format - PHY-Layer Frame Structure (PPDU) Preamble Sequence 5 octets ...

  • Page 80

    Received frames with a frame length field set to 0x00 (invalid PHR) are not signaled to the microcontroller. Table 8-1 on page 80 Table 8-1. 8.1.2 MAC Protocol Layer Data Unit (MPDU) Figure 8-2 on page 80 Figure 8-2. IEEE ...

  • Page 81

    Bit [2:0]: describes the frame type. 802.15.4, section 7.2.1.1.1. Table 8-2. Frame Control Field Bit Assignments Frame Type Value 100 - 111 This subfield is used for address filtering by the third level filter rules. Only frame types 0 ...

  • Page 82

    Bit 6: the "Intra-PAN" subfield indicates that in a frame, where both, the destination and source addresses are present, the PAN-ID of the source address field is omitted. In RX_AACK mode, this bit is evaluated by the address filter ...

  • Page 83

    Bit [15:14]: the "Source Addressing Mode" subfield, with similar meaning as "Destination Addressing Mode", see Table 8-3 on page The subfields of the FCF (Bits 0- 10-15) affect the address filter logic of the AT86RF231 while operating ...

  • Page 84

    Auxiliary Security Header Field The Auxiliary Security Header specifies information required for security processing and has a variable length. This field determines how the frame is actually protected (security level) and which keying material from the MAC security PIB ...

  • Page 85

    Frame Check Sequence (FCS) The Frame Check Sequence (FCS) is characterized by: • Indicate bit errors, based on a cyclic redundancy check (CRC) of length 16 bit • Uses International Telecommunication Union (ITU) CRC polynomial • Automatically evaluated during ...

  • Page 86

    Automatic FCS generation The automatic FCS generation is performed with register bit TX_AUTO_CRC_ON = 1 (reset value). This allows the AT86RF231 to compute the FCS autonomously. For a frame with a frame length specified ≤ N ...

  • Page 87

    Register Description Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit 7 6 +0x04 PA_EXT_EN IRQ_2_EXT_EN Read/Write R/W R/W Reset Value 0 0 • Bit ...

  • Page 88

    Bit 7 - RX_CRC_VALID Reading this register bit indicates whether the last received frame has a valid FCS or not. The register bit is updated when issuing interrupt IRQ_3 (TRX_END) and remains valid until the next TRX_END interrupt is ...

  • Page 89

    Received Signal Strength Indicator (RSSI) The Received Signal Strength Indicator is characterized by: • Minimum RSSI level is -91 dBm (RSSI_BASE_VAL) • Dynamic range • Minimum RSSI value is 0 • Maximum RSSI value is 28 ...

  • Page 90

    Figure 8- -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 8.3.4 Register Description Register 0x06 (PHY_RSSI): Bit +0x06 Read/Write Reset Value • Bit 7 - RX_CRC_VALID Refer to register description in • Bit [6:5] - RND_VALUE ...

  • Page 91

    Energy Detection (ED) The Energy Detection (ED) module is characterized by: • 85 unique energy levels defined • resolution 8.4.1 Overview The receiver ED measurement is used by the network layer as part of a channel selection ...

  • Page 92

    Data Interpretation The PHY_ED_LEVEL is an 8-bit register. The ED value of the AT86RF231 has a valid range from 0x00 to 0x54 with a resolution of 1 dB. All other values do not occur; a value of 0xFF indi- ...

  • Page 93

    Register Description Register 0x07 (PHY_ED_LEVEL): The PHY_ED_LEVEL register contains the result measurement. Bit +0x07 Read/Write Reset Value • Bit [7:0] - ED_LEVEL The minimum ED value (ED_LEVEL = 0) indicates receiver power less than or equal ...

  • Page 94

    Clear Channel Assessment (CCA) The main features of the Clear Channel Assessment (CCA) module are: • All 4 modes are available as defined by IEEE 802.15.4-2006 in section 6.9.9 • Adjustable threshold for energy detection algorithm 8.5.1 Overview A ...

  • Page 95

    Data Interpretation The current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible in register 0x01 (TRX_STATUS). Note, register bits CCA_DONE and CCA_STATUS are cleared in response to a CCA_REQUEST. The completion of a measurement cycle is ...

  • Page 96

    Table 8- Note recommended to perform CCA measurements in RX_ON state only. To avoid switching accidentally to BUSY_RX state the SHR detection can be disabled by setting register bit RX_PDT_DIS (register 0x15, RX_SYN), refer to receiver ...

  • Page 97

    Register Description Register 0x01 (TRX_STATUS): Two register bits of register 0x01 (TRX_STATUS) signal the status of the CCA measurement. Bit 7 6 +0x01 CCA_DONE CCA_STATUS Read/Write R R Reset Value 0 0 • Bit 7 - CCA_DONE This register ...

  • Page 98

    CCA_STATUS (register 0x01, TRX_STATUS) are updated after a CCA_REQUEST. The regis- ter bit is automatically cleared after requesting a CCA measurement with CCA_REQUEST = 1. • Bit [6:5] - CCA_MODE The CCA mode can be selected using register bits CCA_MODE. ...

  • Page 99

    Link Quality Indication (LQI) According to IEEE 802.15.4, the LQI measurement is a characterization of the strength and/or quality of a received packet. The measurement may be implemented using receiver ED, a sig- nal-to-noise ratio estimation combination ...

  • Page 100

    LQI value. Since the packet error rate is a statistical value, the PER shown in “Conditional Packet Error Rate versus LQI” on page 99 tions. A reliable estimation of the packet error rate cannot be based on a single ...

  • Page 101

    Module Description 9.1 Receiver (RX) 9.1.1 Overview The AT86RF231 receiver is split into an analog radio front end and a digital base band proces- sor (RX BBP), see Figure 9-1. RFP RFN The differential RF signal is amplified by ...

  • Page 102

    Frame Receive Procedure The frame receive procedure including the radio transceiver setup for reception and reading PSDU data from the Frame Buffer is described in page 126. 9.1.3 Configuration In Basic Operating Mode the receiver is enabled by writing ...

  • Page 103

    Register Description Register 0x15 (RX_SYN): This register controls the sensitivity threshold of the receiver. Bit 7 6 +0x15 RX_PDT_DIS R/W R Read/Write Reset Value 0 0 • Bit 7 - RX_PDT_DIS RX_PDT_DIS = 1 prevents the reception of a ...

  • Page 104

    Transmitter (TX) 9.2.1 Overview The AT86RF231 transmitter consists of a digital base band processor (TX BBP) and an analog radio front end, see Figure 9-2. DIG3/4 RFP RFN The TX BBP reads the frame data from the Frame Buffer ...

  • Page 105

    Figure 9-3. TX Power Ramping 0 2 TRX_STATE PLL_ON SLP_TR PA buffer PA Modulation When using an external RF front-end (refer to may be required to adjust the startup time of the external PA relative to the internal building blocks ...

  • Page 106

    Bit [5:4] - PA_LT These register bits control the enable lead time of the internal PA relative to the beginning of the transmitted frame. Table 9-3. Register Bits PA_LT • Bit [3:0] - TX_PWR These register bits determine the ...

  • Page 107

    Frame Buffer The AT86RF231 contains a 128 byte dual port SRAM. One port is connected to the SPI inter- face, the other to the internal transmitter and receiver modules. For data communication, both ports are independent and simultaneously accessible. ...

  • Page 108

    User accessible Frame Content The AT86RF231 supports an IEEE 802.15.4 compliant frame format as shown in page 108. Figure 9-4. AT86RF231 Frame Structure Length [octets] 0 Frame Preamble Sequence Duration 4 octets / 128 µs SHR not accesible Access ...

  • Page 109

    Interrupt Handling Access conflicts may occur when reading and writing data simultaneously at the two indepen- dent ports of the Frame Buffer, TX/RX BBP and SPI. Both of these ports have their own address counter that points to the ...

  • Page 110

    Voltage Regulators (AVREG, DVREG) The main features of the Voltage Regulator blocks are: • Bandgap stabilized 1.8V supply for analog and digital domain • Low dropout (LDO) voltage regulator • Configurable for usage of external voltage regulator 9.4.1 Overview ...

  • Page 111

    Register Description Register 0x10 (VREG_CTRL): This register controls the use of the voltage regulators and indicates the status of these. Bit 7 6 +0x10 AVREG_EXT AVDD_OK Read/Write R/W R Reset Value 0 0 • Bit 7 - AVREG_EXT If ...

  • Page 112

    Bit 2 - DVDD_OK This register bit indicates if the internal 1.8V regulated voltage supply DVDD has settled. The bit is set to logic high, if DVREG_EXT = 1. Table 9-8. Register Bit DVDD_OK Note • While the reset ...

  • Page 113

    Battery Monitor (BATMON) The main features of the battery monitor are: • Configurable voltage threshold range: 1.7V to 3.675V • Generates an interrupt when supply voltage drops below a threshold 9.5.1 Overview The battery monitor (BATMON) detects and indicates ...

  • Page 114

    Interrupt Handling A supply voltage drop below the configured threshold value is indicated by an interrupt IRQ_7 (BAT_LOW), see if BATMON_OK changes from interrupt is generated when: • The battery voltage is under the default ...

  • Page 115

    Bit [3:0] - BATMON_VTH The threshold values for the battery monitor are set by register bits BATMON_VTH: Table 9-11. BATMON_VTH[3:0] 8111C–MCU Wireless–09/09 Battery Monitor Threshold Voltage Value Voltage [V] BATMON_HR = 1 0x0 2.550 0x1 2.625 0x2 2.700 0x3 ...

  • Page 116

    Crystal Oscillator (XOSC) The main crystal oscillator features are: • 16 MHz amplitude controlled crystal oscillator • 330 µs typical settling time after leaving SLEEP state • Configurable trimming capacitance array • Configurable clock output (CLKM) 9.6.1 Overview The ...

  • Page 117

    To calculate the total load capacitance, the following formula can be used 0 The trimming capacitors provide the possibility of reducing frequency deviations caused by pro- duction process variations or by external components ...

  • Page 118

    Note: • During reset procedure, see shadowed. Although the clock setting of CLKM remains after reset, a read access to register bits CLKM_CTRL delivers the reset value 1. For that reason it is recommended to write the previous configuration (before ...

  • Page 119

    Bit [2:0] - CLKM_CTRL These register bits set clock rate of pin 17 (CLKM). Table 9-14. Register Bit CLKM_CTRL Register 0x12 (XOSC_CTRL): The register XOSC_CTRL controls the operation of the crystal oscillator Bit +0x12 XTAL_MODE Read/Write R/W ...

  • Page 120

    Bit [3:0] - XTAL_TRIM The register bits XTAL_TRIM control two internal capacitance arrays connected to pins XTAL1 and XTAL2. A capacitance value in the range from 4 selectable with a resolution of 0.3 pF. ...

  • Page 121

    Frequency Synthesizer (PLL) The main PLL features are: • Generate RX/TX frequencies for all IEEE 802.15.4 - 2.4 GHz channels • Autonomous calibration loops for stable operation within the operating range • Two PLL-interrupts for status indication • Fast ...

  • Page 122

    If the PLL operates for a long time on the same channel, e.g. more than 5 min, or the operating temperature changes significantly recommended to initiate the calibration loops manually. Both calibration loops can be initiated manually by ...

  • Page 123

    Table 9-17. Register Bit CHANNEL Register 0x1A (PLL_CF): This register controls the operation of the center frequency calibration loop. Bit 7 6 +0x1A PLL_CF_START Read/Write R/W R/W Reset Value 0 1 • Bit 7 - PLL_CF_START PLL_CF_START = 1 initiates ...

  • Page 124

    Bit 7 - PLL_DCU_START PLL_DCU_START = 1 initiates the delay cell calibration. The calibration cycle has finished after at most t ing the calibration. • Bit [6:0] - Reserved 8111C–MCU Wireless–09/ µs, the register bit is set ...

  • Page 125

    Automatic Filter Tuning (FTN) 9.8.1 Overview The FTN is incorporated to compensate device tolerances for temperature, supply voltage varia- tions as well as part-to-part variations of the radio transceiver. The filter-tuning result is used to correct the analog baseband ...

  • Page 126

    Radio Transceiver Usage This section describes basic procedures to receive and transmit frames using the AT86RF231. For a detailed programming description refer to reference [6]. 10.1 Frame Receive Procedure A frame reception comprises of two actions: The PHY listens ...

  • Page 127

    Frame Transmit Procedure A frame transmission comprises of two actions, a Frame Buffer write access and the transmis- sion of the Frame Buffer content. Both actions can be run in parallel if required by critical protocol timing. Figure 10-2 ...

  • Page 128

    AT86RF231 Extended Feature Set 11.1 Security Module (AES) The security module (AES) is characterized by: • Hardware accelerated encryption and decryption • Compatible with AES-128 standard (128-bit key and data block size) • ECB (encryption/decryption) mode and CBC (encryption) ...

  • Page 129

    The encryption or decryption is initiated with register bit AES_REQUEST = 1 (SRAM address 0x83, AES_CTRL or the mirrored version with SRAM address 0x94, AES_CTRL_MIRROR). The AES module control registers are only accessible using SRAM read and write accesses on ...

  • Page 130

    A security operation can be started within one SRAM access by appending the start command AES_REQUEST = 1 (register 0x94, AES_CTRL_MIRROR) to the SPI sequence. Register AES_CTRL_MIRROR is a mirrored version of register 0x83 (AES_CTRL). Figure 11-1. ECB Programming SPI ...

  • Page 131

    When decrypting, due to the nature of AES algorithm, the initial key to be used is not the same as the one used for encryption, but rather the last round key instead. This last round key is the content of ...

  • Page 132

    Note that IEEE 802.15.4-2006 standard MIC algorithm requires CBC mode encryption only implements a one-way hash function. 11.1.5 Data Transfer - Fast SRAM Access The ECB and CBC modules including the AES core are clocked with 16 MHz. ...

  • Page 133

    Start of Security Operation and Status A security operation is started within one SRAM access by appending the start command AES_REQUEST = 1 (register 0x94, AES_CTRL_MIRROR) to the SPI sequence. Register AES_CTRL_MIRROR is a mirrored version of register 0x83 ...

  • Page 134

    Table 11-3. Register Bit AES_ER • Bit [6:1] -Reserved • Bit 0 - AES_DONE Table 11-4. Register Bit AES_DONE Register 0x83 (AES_CTRL): This register controls the operation of the security module. Do not access this register during AES operation to ...

  • Page 135

    Bits 3 - AES_DIR This register bit sets the AES operation direction, either encryption or decryption. Table 11-7. Register Bit AES_DIR • Bit [2:0] - Reserved Register 0x94 (AES_CTRL_MIRROR): Register 0x94 is a mirrored version of register 0x83 (AES_CTRL), ...

  • Page 136

    Random Number Generator 11.2.1 Overview The AT86RF231 incorporates a 2-bit truly random number generator by observation of noise. This random number can be used to: • Generate random seeds for CSMA-CA algorithm • Generate random values for AES key ...

  • Page 137

    High Data Rate Modes The main features are: • High Data Rate Transmission Mb/s. • Support of Basic and Extended Operating Mode • Support of other features of the Extended Feature Set • Reduced ACK timing ...

  • Page 138

    Figure 11-6. High Data Rate Frame Structure 0 192 512 250 kb/s PSDU: 80 octets 500 kb/s PSDU: 80 octets 1000 kb/s PSDU: 80 octets 2000 kb/s PSDU: 80 octets Due to the overhead caused by the SHR, PHR as ...

  • Page 139

    Frame Buffer read access the last byte transferred after the PSDU data is the ED value rather than the LQI value. Figure 11-8 on page 139 access. Figure 11-8. Packet Structure - High Data Rate Frame Buffer Read Access ...

  • Page 140

    Figure 11-9. High Data Rate AACK Timing 0 AACK_ACK_TIME = 0 AACK_ACK_TIME = 1 If register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) is set the acknowledgment time is reduced from 192 µ µs. 11.3.6 Register Description Register 0x0C (TRX_CTRL_2): ...

  • Page 141

    Register 0x17 (XAH_CTRL_1): The XAH_CTRL_1 register is a multi-purpose control register for various RX_AACK settings. Bit 7 6 +0x17 Reserved AACK_FLTR_RES_FT Read/Write R/W R Reset Value 0 0 • Bit [7:6] - Reserved • Bit 5 - AACK_FLTR_RES_FT Refer to ...

  • Page 142

    Antenna Diversity The Antenna Diversity implementation is characterized by: • Improves signal path robustness between nodes • AT86RF231 self-contained antenna diversity algorithm • Direct register based antenna selection 11.4.1 Overview Due to multipath propagation effects between network nodes, the ...

  • Page 143

    Generally, the Antenna Diversity algorithm is enabled with register bit ANT_DIV_EN (register 0x0D, ANT_DIV) set. In this case the control of an antenna diversity switch must be enabled by register bit ANT_EXT_SW_EN (register 0x0D, ANT_DIV). The internal connection to digital ...

  • Page 144

    Bit [3:0] - PDT_THRES These register bits control the sensitivity of the receiver correlation unit. If the Antenna Diversity algorithm is enabled (ANT_DIV_EN = 1), the value shall be set to PDT_THRES = 3, otherwise it shall be set ...

  • Page 145

    Table 11-12. Antenna Diversity Control Register Bit ANT_DIV_EN Note: • Bit 2 - ANT_EXT_SW_EN If enabled, pin 9 (DIG1) and pin 10 (DIG2) become output pins and provide a differential control signal for an Antenna Diversity switch. The selection of ...

  • Page 146

    Table 11-14. Antenna Diversity Switch Control ANT_CTRL Note: 8111C–MCU Wireless–09/09 0 Reserved 1 Antenna 1 DIG1 = L DIG2 = H 2 Antenna 0 DIG1 = H DIG2 = L 3 Default value for ANT_EXT_SW_EN = 0. Mandatory setting for ...

  • Page 147

    RX/TX Indicator The main features are: • RX/TX Indicator to control an external RF Front-End • Microcontroller independent RF Front-End Control • Provide TX Timing Information 11.5.1 Overview While IEEE 802.15 low cost, low power standard, solutions ...

  • Page 148

    The modulation starts 16 µs after the rising edge of SLP_TR. During this time, the PA buffer and the internal PA are enabled. The control of an external PA is done via differential ...

  • Page 149

    Bit 1 - IRQ_MASK_MODE Refer to • Bit 0 - IRQ_POLARITY Refer to 8111C–MCU Wireless–09/09 Section 6.6 “Interrupt Logic” on page Section 6.6 “Interrupt Logic” on page AT86RF231 29. 29. 149 ...

  • Page 150

    RX Frame Time Stamping 11.6.1 Overview To determine the exact timing of an incoming frame, e.g. for beaconing networks, the reception of this frame can be signaled to the microcontroller via pin 10 (DIG2). The pin turns from L ...

  • Page 151

    Register Description Register 0x04 (TRX_CTRL_1): Register 0x04 (TRX_CTRL_1 multi purpose register to control various operating modes and settings of the radio transceiver. Bit 7 6 +0x04 PA_EXT_EN IRQ_2_EXT_EN TX_AUTO_CRC_ON Read/Write R/W R/W Reset Value 0 0 • ...

  • Page 152

    Frame Buffer Empty Indicator 11.7.1 Overview For time critical applications that want to start reading the frame data as early as possible, the Frame Buffer status can be indicated to the microcontroller through a dedicated pin. This pin indicates ...

  • Page 153

    Register Description Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit 7 6 +0x04 PA_EXT_EN IRQ_2_EXT_EN TX_AUTO_CRC_ON Read/Write R/W R/W Reset Value 0 0 • ...

  • Page 154

    Dynamic Frame Buffer Protection 11.8.1 Overview The AT86RF231 continues the reception of incoming frames as long any receive state. When a frame was successfully received and stored into the Frame Buffer, the following frame will ...

  • Page 155

    Configurable Start-Of-Frame Delimiter 11.9.1 Overview The SFD is a field indicating the end of the SHR and the start of the packet data. The length of the SFD is 1 octet (2 symbols). This octet is used for byte ...

  • Page 156

    Electrical Characteristics 12.1 Absolute Maximum Ratings Note: Table 12-1. Absolute Maximum Ratings No. Symbol Parameter 12.1.1 T Storage temperature STOR 12.1.2 T Lead temperature LEAD 12.1.3 V ESD robustness ESD 12.1.4 P Input RF level RF 12.1.5 V Voltage ...

  • Page 157

    Digital Pin Characteristics .Test Conditions: T Table 12-3. Digital Pin Characteristics No. Symbol Parameter 12.3.1 V High level input voltage IH 12.3.2 V Low level input voltage IL 12.3.3 V High level output voltage OH 12.3.4 V Low level ...

  • Page 158

    Table 12-4. Digital Interface Timing Characteristics (Continued) 12.4.15 t BFBP IRQ latency 13 12.4.17 t Interrupt event latency IRQ 12.4.18 f Clock frequency at pin 17 (CLKM) CLKM Notes: 1. Maximum pulse width less than (TX frame length + 16 ...

  • Page 159

    Transmitter Characteristics Test Conditions (unless otherwise stated 3.0V Table 12-6. Transmitter Characteristics No. Symbol Parameter 12.6 Output power TX 12.6.2 P Output power range RANGE 12.6.3 P Output power tolerance ACC 12.6.4 TX ...

  • Page 160

    Receiver Characteristics Test Conditions (unless otherwise stated 3.0V ure 5-1 on page Table 12-7. Receiver Characteristics No. Symbol Parameter 12.7.1 P Receiver sensitivity SENS 250 kb/s 500 kb/s 1000 kb/s 2000 kb/s Antenna Diversity 12.7.2 ...

  • Page 161

    Current Consumption Specifications Test Conditions (unless otherwise stated 3.0V Table 12-8. Current Consumption Specifications No. Symbol Parameter 12.8.1 I Supply current transmit state BUSY_TX 12.8.2 I Supply current RX_ON state RX_ON 12.8.3 I Supply current ...

  • Page 162

    Typical Characteristics 13.1 Active Supply Current The following charts showing each a typical behavior of the AT86RF231. These figures are not tested during manufacturing. All power consumption measurements are performed with pin 17 (CLKM) disabled, unless otherwise stated. The ...

  • Page 163

    Figure 13-2. Current Consumption in TRX_OFF State 13.1.2 PLL_ON state Figure 13-3. Current Consumption in PLL_ON State 8111C–MCU Wireless–09/09 0.5 0.4 0.3 0.2 0.1 0 1.6 1.8 2.0 2.2 2.4 EVDD [ ...

  • Page 164

    RX_ON state Figure 13-4. Current Consumption in RX_ON State - High Sensitivity Figure 13-5. Current Consumption in RX_ON State - High Input Level 8111C–MCU Wireless–09/ ...

  • Page 165

    Figure 13-6. Current Consumption in RX_ON State - Reduced Sensitivity 13.1.4 TX_BUSY state Figure 13-7. Current Consumption in TX_BUSY State - Minimum Output Power 8111C–MCU Wireless–09/ ...

  • Page 166

    Figure 13-8. Current Consumption in TX_BUSY State - Output Power 0 dBm Figure 13-9. Current Consumption in TX_BUSY State - Maximum Output Power 8111C–MCU Wireless–09/ 1.6 1.8 2.0 2.2 2.4 EVDD [V] ...

  • Page 167

    SLEEP Figure 13-10. Current Consumption in SLEEP 13.2 State Transition Timing Figure 13-11. Transition Time from EVDD to P_ON (CLKM available) 8111C–MCU Wireless–09/09 1000 100 10 1 0.1 1.6 1.8 2.0 2.2 2.4 500 450 400 350 300 250 ...

  • Page 168

    Figure 13-12. Transition Time from SLEEP to TRX_OFF (IRQ_4 (AWAKE_END)) Figure 13-13. Transition Time from TRX_OFF to PLL_ON 8111C–MCU Wireless–09/09 500 450 400 350 300 250 200 150 100 50 0 1.6 1.8 2.0 2.2 2.4 EVDD [V] 140 120 ...

  • Page 169

    Register Summary The AT86RF231 provides a register space of 64 8-bit registers, used to configure, control and monitor the radio transceiver. Note: Addr Name Bit7 Bit6 0x00 - - 0x01 TRX_STATUS CCA_DONE CCA_STATUS 0x02 TRX_STATE TRAC_STATUS[2] TRAC_STATUS[1] 0x03 TRX_CTRL_0 ...

  • Page 170

    CSMA_SEED_0 CSMA_SEED_0[7] CSMA_SEED_0[6] 0x2E CSMA_SEED_1 AACK_FVN_MODE[1] AACK_FVN_MODE[0] 0x2F CSMA_BE MAX_BE[3] MAX_BE[2] .... - - The reset values of the AT86RF231 registers in state P_ON page 170. Note: Table 14-1. Register Summary - Reset Values Address Reset Value Address 0x00 ...

  • Page 171

    Abbreviations AACK ACK ADC AD AGC AES ARET AVREG AWGN BATMON BBP BPF CBC CRC CCA CSMA-CA CW DFBP DVREG ECB ED ESD EVM FCF FCS FIFO FTN GPIO ISM LDO LNA LO LQI LSB MAC 8111C–MCU Wireless–09/09 - ...

  • Page 172

    MFR MHR MISO MOSI MSB MSDU MPDU MSK O-QPSK PA PAN PCB PER PHR PHY PLL POR PPF PRBS PSDU PSD QFN RF RSSI RX SCLK /SEL SFD SHR SPI SRAM SSBF TX VCO VREG XOSC 8111C–MCU Wireless–09/09 - MAC ...

  • Page 173

    Ordering Information Ordering Code Package AT86RF231-ZU QN AT86RF231-ZF QN Package Type Description QN 32QN2, 32 lead 5.0x5.0 mm Body, 0.50 mm Pitch, Quad Flat No-lead Package (QFN) Sawn Note: 17. Soldering Information Recommended soldering profile is specified in IPC/JEDEC ...

  • Page 174

    Package Drawing - 32QN2 E Top View Top View E2 E2 Bottom View Bottom View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-220, Variation VHHD-6, for proper dimensions, tolerances, datums, etc. 2. Dimension ...

  • Page 175

    Appendix A - Continuous Transmission Test Mode 20.1 Overview The AT86RF231 offers a Continuous Transmission Test Mode to support final application / pro- duction tests as well as certification tests. Using this test mode the radio transceiver transmits continuously ...

  • Page 176

    Note: The content of the Frame Buffer has to be defined for Continuous Transmission PRBS mode or CW mode. To measure the power spectral ...

  • Page 177

    Register Description Register 0x36 (TST_CTRL_DIGI): Register TST_CTRL_DIG enables the continuous transmission test mode. Bit 7 6 +0x36 Reserved Read/Write R/W R/W Reset Value 0 0 • Bit [7:4] - Reserved • Bit [3:0] - TST_CTRL_DIG These register bits enable ...

  • Page 178

    Appendix B - AT86RF231-ZF Extended Temperature Range 21.1 Introduction Appendix B contains information specific to devices operating at temperatures up to 125°C. Only deviations to the standard device AT86RF231-ZU are covered in this appendix, all other infor- mation are ...

  • Page 179

    Typical Characteristics The following charts showing each a typical behavior of the AT86RF231. These figures are not tested during manufacturing for all supply voltages and all temperatures. All power consumption measurements are performed with pin 17 (CLKM) disabled, unless ...

  • Page 180

    Figure 21-2. Current Consumption in TRX_OFF State 21.4.2 PLL_ON state Figure 21-3. Current Consumption in PLL_ON State 8111C–MCU Wireless–09/09 0.5 0.4 0.3 0.2 0.1 0 1.6 1.8 2.0 2.2 2.4 EVDD [ ...

  • Page 181

    RX_ON state Figure 21-4. Current Consumption in RX_ON State - High Sensitivity Figure 21-5. Current Consumption in RX_ON State - High Input Level 8111C–MCU Wireless–09/ ...

  • Page 182

    Figure 21-6. Current Consumption in RX_ON State - Reduced Sensitivity 21.4.4 TX_BUSY state Figure 21-7. Current Consumption in TX_BUSY State - Minimum Output Power 8111C–MCU Wireless–09/ ...

  • Page 183

    Figure 21-8. Current Consumption in TX_BUSY State - Output Power 0 dBm Figure 21-9. Current Consumption in TX_BUSY State - Maximum Output Power 8111C–MCU Wireless–09/ 1.6 1.8 2.0 2.2 2.4 ...

  • Page 184

    SLEEP Figure 21-10. Current Consumption in SLEEP 8111C–MCU Wireless–09/09 10000 1000 100 10 1 0.1 1.6 1.8 2.0 2.2 2.4 AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 EVDD [V] 125 °C 85 °C 25 °C -40 °C 3.8 184 ...

  • Page 185

    State Transition Timing Figure 21-11. Transition Time from EVDD to P_ON (CLKM available) Figure 21-12. Transition Time from SLEEP to TRX_OFF (IRQ_4 (AWAKE_END)) 8111C–MCU Wireless–09/09 500 450 400 350 300 250 200 150 100 50 0 1.6 1.8 2.0 ...

  • Page 186

    Figure 21-13. Transition Time from TRX_OFF to PLL_ON 8111C–MCU Wireless–09/09 140 120 100 1.6 1.8 2.0 2.2 2.4 EVDD [V] AT86RF231 2.6 2.8 3.0 3.2 3.4 3.6 -40 °C 25 °C 85 °C 125 °C ...

  • Page 187

    Receiver Performance 21.6.1 Sensitivity Figure 21-14. Sensitivity 21.6.2 Adjacent & Alternate Channel Selectivity (ACRx) Figure 21-15. Adjacent and Alternate Channel Selectivity 8111C–MCU Wireless–09/09 -89 -91 -93 -95 -97 -99 -101 -103 -105 1.6 1.8 2.0 2.2 2 ...

  • Page 188

    RSSI Figure 21-16. RSSI 8111C–MCU Wireless–09/ -100 -90 -80 -70 -60 RX Input Level [dBm] AT86RF231 -50 -40 -30 -20 -10 -40 °C 25 °C 85 °C 125 °C 0 188 ...

  • Page 189

    Transmitter Performance 21.7.1 TX Output Power vs. TX Power Level Figure 21-17. TX Output Power vs. TX_PWR (EVDD = 3.0V, CH=19) 21.7.2 TX Output Power vs. EVDD Figure 21-18. TX Output Power vs. EVDD (TX_PWR = 0, CH=19) 8111C–MCU ...

  • Page 190

    TX Output Power vs. Channel Figure 21-19. TX Output Power vs. Channel (EVDD = 3.0V, TX_PWR = 0) 8111C–MCU Wireless–09/09 4 3.5 3 2.5 2 1 Channel acct. ...

  • Page 191

    TX EVM vs. EVDD Figure 21-20. Error Vector Magnitude (EVM) vs. EVDD (TX_PWR = 0, CH=19) 8111C–MCU Wireless–09/ 1.6 1.8 2.0 2.2 2.4 EVDD [V] AT86RF231 2.6 2.8 ...

  • Page 192

    Appendix C - Errata 22.1 AT86RF231 Rev.A No known errata 8111C–MCU Wireless–09/09 AT86RF231 192 ...

  • Page 193

    Revision history 23.1 Rev.8111C - 09/ 23.2 Rev.8111B - 02/ 23.3 Rev.8111A - 05/08 1. Initial revision 8111C–MCU Wireless–09/09 Updated the datasheet with a new device Added “Appendix B - AT86RF231-ZF Extended Temperature ...

  • Page 194

    References [1] [2] [3] [4] [5] [6] 8111C–MCU Wireless–09/09 IEEE Std 802.15.4™-2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs) IEEE Std 802.15.4™-2003: Wireless Medium Access Control (MAC) and Physical Layer ...

  • Page 195

    Table of Contents Features ..................................................................................................... 1 1 Pin-out Diagram ....................................................................................... 2 2 Disclaimer ................................................................................................. 9 3 Overview ................................................................................................... 9 4 General Circuit Description .................................................................. 10 5 Application Circuits ............................................................................... 12 6 Microcontroller Interface ....................................................................... 16 7 Operating Modes .................................................................................... 33 ...

  • Page 196

    Radio Transceiver Usage .................................................................... 126 11 AT86RF231 Extended Feature Set ...................................................... 128 12 Electrical Characteristics .................................................................... 156 13 Typical Characteristics ........................................................................ 162 14 Register Summary ............................................................................... 169 15 Abbreviations ....................................................................................... 171 8111C–MCU Wireless–09/09 9.3 Frame Buffer ..................................................................................................107 9.4 Voltage ...

  • Page 197

    Ordering Information ........................................................................... 173 17 Soldering Information .......................................................................... 173 18 Package Thermal Properties ............................................................... 173 19 Package Drawing - 32QN2 ................................................................... 174 20 Appendix A - Continuous Transmission Test Mode ......................... 175 21 Appendix B - AT86RF231-ZF Extended Temperature ...

  • Page 198

    ... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2009 Atmel Corporation. All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia Atmel Europe Unit 1-5 & ...