ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 19
ATmega1284PR231
Manufacturer Part Number
ATmega1284PR231
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT86RF231.pdf
(198 pages)
2.ATMEGA1284PR231.pdf
(380 pages)
3.ATMEGA1284PR231.pdf
(20 pages)
Specifications of ATmega1284PR231
Flash (kbytes)
128 Kbytes
Max. Operating Frequency
20 MHz
Max I/o Pins
32
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
16
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
3
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
2
Antenna Diversity
Yes
External Pa Control
Yes
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
13.2
Transmit Current Consumption (ma)
14.4
Link Budget (dbm)
104
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6.2
Table 6-2.
6.2.1
8111C–MCU Wireless–09/09
Bit 7
1
1
0
0
0
0
SPI Protocol
Register Access Mode
Bit 6
0
1
0
1
0
1
SPI Command Byte definition
Bit 5
1
1
0
0
Each SPI sequence starts with transferring a command byte from the SPI master via MOSI (see
Table 6-2 on page
additional mode-dependent information.
Each SPI transfer returns bytes back to the SPI master on MISO. The content of the first byte
(see value "PHY_STATUS" in
after reset. To transfer status information of the radio transceiver to the microcontroller, the con-
tent of the first byte can be configured with register bits SPI_CMD_MODE (register 0x04,
TRX_CTRL_1). For details, refer to
24.
In
stated with XX on MOSI are ignored by the radio transceiver, but need to have a valid logic level.
Return values on MISO stated as XX shall be ignored by the microcontroller.
The different access modes are described within the following sections.
A register access mode is a two-byte read/write operation initiated by /SEL = L. The first trans-
ferred byte on MOSI is the command byte including an identifier bit (bit7 = 1), a read/write select
bit (bit 6), and a 6-bit register address.
On read access, the content of the selected register address is returned in the second byte on
MISO (see
Figure 6-4.
Note:
On write access, the second byte transferred on MOSI contains the write data to the selected
address (see
Bit 4
Figure 6-4 on page 19
Register address [5:0]
Register address [5:0]
1. Each SPI access can be configured to return radio controller status information
Bit 3
Figure 6-4 on page
(PHY_STATUS) on MISO, for details refer to
tion” on page
MOSI
MISO
Figure 6-5 on page
Packet Structure - Register Read Access
Reserved
Reserved
Reserved
Reserved
Bit 2
19) with MSB first. This command byte defines the SPI access mode and
1
24.
Bit 1
byte 1 (command byte)
0
to
PHY_STATUS
Figure 6-14 on page 23
Figure 6-4 on page 19
19).
ADDRESS[5:0]
Bit 0
20).
Section 6.3.1 “Register Description - SPI Control” on page
Access Mode
Register access
Frame Buffer access
SRAM access
(1)
Section 6.3 “Radio Transceiver Status informa-
to
and the following chapters logic values
Figure 6-14 on page
READ DATA[7:0]
byte 2 (data byte)
XX
Access Type
Read access
Write access
Read access
Write access
Read access
Write access
AT86RF231
23) is set to zero
19
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