ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 122
ATmega1284PR231
Manufacturer Part Number
ATmega1284PR231
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT86RF231.pdf
(198 pages)
2.ATMEGA1284PR231.pdf
(380 pages)
3.ATMEGA1284PR231.pdf
(20 pages)
Specifications of ATmega1284PR231
Flash (kbytes)
128 Kbytes
Max. Operating Frequency
20 MHz
Max I/o Pins
32
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
16
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
3
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
2
Antenna Diversity
Yes
External Pa Control
Yes
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
13.2
Transmit Current Consumption (ma)
14.4
Link Budget (dbm)
104
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9.7.5
9.7.6
8111C–MCU Wireless–09/09
Bit
+0x08
Read/Write
Reset Value
Interrupt Handling
Register Description
CCA_REQUEST
7
W
0
If the PLL operates for a long time on the same channel, e.g. more than 5 min, or the operating
temperature changes significantly, it is recommended to initiate the calibration loops manually.
Both calibration loops can be initiated manually by setting PLL_CF_START = 1 (register 0x1A,
PLL_CF) and register bit PLL_DCU_START = 1 (register 0x1B, PLL_DCU). To start the calibra-
tion the device must be in PLL_ON or RX_ON state. The completion of the center frequency
tuning is indicated by a PLL_LOCK interrupt.
Both calibration loops may be run simultaneously.
Two different interrupts indicate the PLL status (refer to register 0x0F). IRQ_0 (PLL_LOCK) indi-
cates that the PLL has locked. IRQ_1 (PLL_UNLOCK) interrupt indicates an unexpected unlock
condition. A PLL_LOCK interrupt clears any preceding PLL_UNLOCK interrupt automatically
and vice versa.
A PLL_LOCK interrupt is supposed to occur in the following situations:
Any other occurrences of PLL interrupts indicate erroneous behavior and require checking of the
actual device status.
The state transition from BUSY_TX to PLL_ON after successful transmission does not generate
an IRQ_0 (PLL_LOCK) within the settling period.
Register 0x08 (PHY_CC_CCA):
This register sets the IEEE 802.15.4 - 2.4 GHz channel number
• Bit 7 - CCA_REQUEST
Refer to
• Bit [6:5] - CCA_MODE
Refer to
• Bit [4:0] - CHANNEL
The register bits CHANNEL define the RX/TX channel. The channel assignment is according to
IEEE 802.15.4.
• State change from TRX_OFF to PLL_ON / RX_ON / TX_ARET_ON / RX_AACK_ON
• Channel change in states PLL_ON / RX_ON / TX_ARET_ON / RX_AACK_ON
R/W
6
0
CCA_MODE
Section 8.5 “Clear Channel Assessment (CCA)” on page
Section 8.5 “Clear Channel Assessment (CCA)” on page
R/W
5
1
R/W
4
0
R/W
3
1
CHANNEL
R/W
2
0
R/W
1
94.
94.
1
AT86RF231
R/W
0
1
PHY_CC_CCA
122
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