ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 62

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

7.2.3.6
Figure 7-10. Example Timing of an RX_AACK Transaction for Slotted Operation
7.2.3.7
8111C–MCU Wireless–09/09
Frame Type
TRX_STATE
RX/TX
IRQ
Typ. Processing Delay
SLP_TR
RX_AACK Slotted Operation - Slotted Acknowledgement
RX_AACK Mode Timing
RX_AACK_ON
AT86RF231 supports slotted acknowledgement operation, refer to IEEE 802.15.4-2006, section
7.5.6.4.2, in conjunction with the microcontroller.
In RX_AACK mode with register bit SLOTTED_OPERATION (register 0x2C, XAH_CTRL_0) set,
the transmission of an acknowledgement frame has to be controlled by the microcontroller. If an
ACK frame has to be transmitted, the radio transceiver expects a rising edge on pin 11
(SLP_TR) to actually start the transmission. This waiting state is signaled 6 symbol periods after
the reception of the last symbol of a data or MAC command frame by register bits
TRAC_STATUS (register 0x02, XAH_CTRL_0), which are set to SUCCESS_WAIT_FOR_ACK
in that case. In networks using slotted operation the start of the acknowledgment frame, and
thus the exact timing, must be provided by the microcontroller.
A timing example of an RX_AACK transaction with register bit SLOTTED_OPERATION (register
0x2C, XAH_CTRL_0) set is shown in
ready to transmit 6 symbol times after the reception of the last symbol of a data or MAC com-
mand frame. The transmission of the acknowledgement frame is initiated by the microcontroller
with the rising edge of pin 11 (SLP_TR) and starts t
specified in
12.4.17.
If register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) is set, an acknowledgment frame
can be sent already 2 symbol times after the reception of the last symbol of a data or MAC com-
mand frame.
A timing example of an RX_AACK transaction is shown in
ple a data frame of length 10 with an ACK request is received. The AT86RF231 changes to state
BUSY_RX_AACK after SFD detection. The completion of the frame reception is indicated by a
TRX_END interrupt. Interrupts IRQ_2 (RX_START) and IRQ_5 (AMI) are disabled in this exam-
ple. The ACK frame is automatically transmitted after a default wait period of 12 symbols
(192 µs), register bit AACK_ACK_TIME = 0 (reset value). The interrupt latency t
in
0
Section 12.4 “Digital Interface Timing Characteristics” on page
64
SFD
Section 12.4 “Digital Interface Timing Characteristics” on page
RX
RX
Data Frame (Length = 10, ACK=1)
waiting period signalled by register bits TRAC_STATUS
TRX_END
t
IRQ
512
BUSY_RX_AACK
(6 symbols)
Figure 7-10 on page
96 µs
t
TR10
SLP_TR
704
TR10
ACK transmission initated by microcontroller
= 16 µs later. The interrupt latency t
ACK Frame
Figure 7-11 on page
TX
TX
62. The acknowledgement frame is
157, parameter 12.4.17.
1026
AT86RF231
RX_AACK_ON
RX
RX
time [µs]
63. In this exam-
157, parameter
IRQ
is specified
IRQ
62
is