ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 133
ATmega1284PR231
Manufacturer Part Number
ATmega1284PR231
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT86RF231.pdf
(198 pages)
2.ATMEGA1284PR231.pdf
(380 pages)
3.ATMEGA1284PR231.pdf
(20 pages)
Specifications of ATmega1284PR231
Flash (kbytes)
128 Kbytes
Max. Operating Frequency
20 MHz
Max I/o Pins
32
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
16
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
3
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
2
Antenna Diversity
Yes
External Pa Control
Yes
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
13.2
Transmit Current Consumption (ma)
14.4
Link Budget (dbm)
104
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11.1.6
11.1.7
11.1.8
8111C–MCU Wireless–09/09
Bit
+0x82
Read/Write
Reset Value
Start of Security Operation and Status
SRAM Register Summary
AES SRAM Configuration Register
AES_ER
7
R
0
A security operation is started within one SRAM access by appending the start command
AES_REQUEST = 1 (register 0x94, AES_CTRL_MIRROR) to the SPI sequence. Register
AES_CTRL_MIRROR is a mirrored version of register 0x83 (AES_CTRL).
The status of the security processing is indicated by register 0x82 (AES_STATUS). After 24 µs
AES processing time register bit AES_DONE changes to 1 (register 0x82, AES_STATUS) indi-
cating that the security operation has finished, see parameter 12.4.15 in
Interface Timing Characteristics” on page
The following registers are required to control the security module:
Table 11-2.
These registers are only accessible using SRAM write and read accesses, for details refer to
Section 6.2.3 “SRAM Access Mode” on page
entering the SLEEP state.
Register 0x82 (AES_STATUS):
This read-only register signals the status of the security module and operation.
• Bit 7 - AES_ER
This SRAM register bit indicates an error of the AES module. An error may occur for instance
after an access to SRAM register 0x83 (AES_CTRL) while an AES operation is running or after
reading less than 128 bits from SRAM register space 0x84 - 0x93 (AES_STATE).
SRAM-Addr.
0x80 - 0x81
0x82
0x83
0x84 - 0x93
0x94
0x95 - 0xFF
6
R
0
SRAM Security Module Address Space Overview
5
R
0
Register Name
AES_STATUS
AES_
AES_KEY
AES_STATE
AES_
CTRL
CTRL
4
R
0
_MIRROR
Reserved
3
R
0
157.
Description
Reserved, not available
AES Status
Security Module Control, AES Mode
Depends on AES_MODE setting:
AES_MODE = 1:
- Contains AES_KEY (key)
AES_MODE = 0 | 2:
- Contains AES_STATE (128-bit data block)
Mirror of register 0x83 (AES_
Reserved, not available
22. Note, that the SRAM register are reset when
2
R
0
1
R
0
CTRL
AES_DONE
AT86RF231
Section 12.4 “Digital
0
R
0
)
AES_STATUS
133
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