ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 102

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

9.1.2
9.1.3
8111C–MCU Wireless–09/09
Frame Receive Procedure
Configuration
The frame receive procedure including the radio transceiver setup for reception and reading
PSDU data from the Frame Buffer is described in
page
In Basic Operating Mode the receiver is enabled by writing command RX_ON to register bits
TRX_CMD (register 0x02, TRX_STATE) in states TRX_OFF or PLL_ON. Similarly in Extended
Operating Mode, the receiver is enabled for RX_AACK operation from states TRX_OFF or
PLL_ON by writing the command RX_AACK_ON. There is no additional configuration required
to receive IEEE 802.15.4 compliant frames when using the Basic Operating Mode. However, the
frame reception in the Extended Operating Mode requires further register configurations, for
details refer to
The AT86RF231 receiver has an outstanding sensitivity performance of -101 dBm. At certain
environmental conditions or for High Data Rate Modes, refer to
Modes” on page
adjusting the synchronization header detector threshold using register bits RX_PDT_LEVEL
(register 0x15, RX_SYN). Received signals with an RSSI value below the threshold do not acti-
vate the demodulation process.
Furthermore, it may be useful to protect a received frame against overwriting by subsequent
received frames.
A Dynamic Frame Buffer Protection is enabled with register bit RX_SAFE_MODE (register
0x0C, TRX_CTRL_2) set, see
The receiver remains in RX_ON or RX_AACK_ON state until the whole frame is read by the
microcontroller, indicated by /SEL = H during the SPI Frame Receive Mode. The Frame Buffer
content is only protected if the FCS is valid.
A Static Frame Buffer Protection is enabled with register bit RX_PDT_DIS (register 0x15,
RX_SYN) set. The receiver remains in RX_ON or RX_AACK_ON state and no further SHR is
detected until the register bit RX_PDT_DIS is set back.
126.
Section 7.2 “Extended Operating Mode” on page
137, it may be useful to manually decrease this sensitivity. This is achieved by
Section 11.8 “Dynamic Frame Buffer Protection” on page
Section 10.1 “Frame Receive Procedure” on
47.
Section 11.3 “High Data Rate
AT86RF231
154.
102