ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 152

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

11.7
11.7.1
Figure 11-13. Timing Diagram of Frame Buffer Empty Indicator
8111C–MCU Wireless–09/09
/SEL
SCLK
MOSI
MISO
IRQ
Notes
IRQ_2 (RX_START)
Frame Buffer Empty Indicator
PHY_STATUS
Overview
Command
IRQ_STATUS
XX
For time critical applications that want to start reading the frame data as early as possible, the
Frame Buffer status can be indicated to the microcontroller through a dedicated pin. This pin
indicates to the microcontroller if an access to the Frame Buffer is not possible since valid PSDU
data are missing.
Pin 24 (IRQ) can be configured as a Frame Buffer Empty Indicator during a Frame Buffer read
access. This mode is enabled by register bit RX_BL_CTRL (register 0x04, TRX_CTRL_1). The
IRQ pin turns into Frame Buffer Empty Indicator after the Frame Buffer read access command,
see note (1) in
Buffer read procedure has finished indicated by /SEL = H, see note (4).
The microcontroller has to observe the IRQ pin during the Frame Buffer read procedure. A
Frame Buffer read access can proceed as long as pin IRQ = L, see note (2). Pin IRQ = H indi-
cates that the Frame Buffer is currently not ready for another SPI cycle, note (3), and thus the
Frame Buffer read procedure has to wait for valid data accordingly.
The access indicator pin 24 (IRQ) shows a valid access signal (either access is allowed or
denied) not before t
read command byte.
After finishing the SPI frame receive procedure, and the SPI has been released by /SEL = H,
note (4), pending interrupts are indicated immediately by pin IRQ. During all other SPI accesses,
except during a SPI frame receive procedure with RX_BL_CTRL = 1, pin IRQ only indicates
interrupts.
If a receive error occurs during the Frame Buffer read access the Frame Buffer Empty Indicator
locks on 'empty' (pin IRQ = H) too. To prevent possible deadlocks, the microcontroller should
impose a timeout counter that checks whether the Frame Buffer Empty Indicator remains logic
high for more than 64 µs. Presuming a PHY data rate of 250 kb/s a new byte must have been
arrived at the Frame Buffer during that period. If not, the Frame Buffer read access should be
aborted.
PHY_STATUS
Command
(1)
Figure 11-13 on page
PHR[7:0]
XX
13
= 750 nsec after the rising edge of last SCLK clock of the Frame Buffer
PSDU[7:0]
(2)
XX
Frame Buffer Empty Indicator
(3)
152, has been transferred on the SPI bus until the Frame
PSDU[7:0]
t
13
XX
PSDU[7:0]
XX
LQI[7:0]
XX
(4)
IRQ_3 (TRX_END)
AT86RF231
PHY_STATUS
Command
IRQ_STATUS
XX
152