ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 29

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

6.6
6.6.1
Table 6-9.
8111C–MCU Wireless–09/09
IRQ Name
IRQ_7 (BAT_LOW)
IRQ_6 (TRX_UR)
IRQ_5 (AMI)
IRQ_4 (CCA_ED_DONE)
IRQ_3 (TRX_END)
IRQ_2 (RX_START)
IRQ_1 (PLL_UNLOCK)
IRQ_0 (PLL_LOCK)
Interrupt Logic
Overview
Interrupt Description in Basic Operating Mode
The AT86RF231 differentiates between nine interrupt events (eight physical interrupt registers,
one shared by two functions). Each interrupt is enabled by setting the corresponding bit in the
interrupt mask register 0x0E (IRQ_MASK). Internally, each pending interrupt is stored in a sepa-
rate bit of the interrupt status register. All interrupt events are OR-combined to a single external
interrupt signal (IRQ, pin 24). If an interrupt is issued (pin IRQ = H), the microcontroller shall read
the interrupt status register 0x0F (IRQ_STATUS) to determine the source of the interrupt. A read
access to this register clears the interrupt status register and thus the IRQ pin, too.
Interrupts are not cleared automatically when the event that caused them vanishes. Exceptions
are IRQ_0 (PLL_LOCK) and IRQ_1 (PLL_UNLOCK) because the occurrence of one clears the
other.
The supported interrupts for the Basic Operating Mode are summarized in
29.
The interrupt IRQ_4 has two meanings, depending on the current radio transceiver state, refer to
register 0x01 (TRX_STATUS).
After P_ON, SLEEP, or RESET, the radio transceiver issues an interrupt IRQ_4 (AWAKE_END)
when it enters state TRX_OFF.
The second meaning is only valid for receive states. If the microcontroller initiates an energy-
detect (ED) or clear-channel-assessment (CCA) measurement, the completion of the measure-
ment is indicated by interrupt IRQ_4 (CCA_ED_DONE), refer to
Handling” on page 92
After P_ON or RESET all interrupts are disabled. During radio transceiver initialization it is rec-
ommended to enable IRQ_4 (AWAKE_END) to be notified once the TRX_OFF state is entered.
Description
Indicates a supply voltage below the programmed threshold.
Indicates a Frame Buffer access violation.
Indicates address matching.
Multi-functional interrupt:
1. AWAKE_END:
2. CCA_ED_DONE:
RX: Indicates the completion of a frame reception.
TX: Indicates the completion of a frame transmission.
Indicates the start of a PSDU reception. The TRX_STATE changes to BUSY_RX, the PHR is
valid to read from Frame Buffer.
Indicates PLL unlock. If the radio transceiver is BUSY_TX / BUSY_TX_ARET state, the PA is
turned off immediately.
Indicates PLL lock.
• Indicates radio transceiver reached TRX_OFF state after P_ON, RESET, or SLEEP states.
• Indicates the end of a CCA or ED measurement.
and
Section 8.5.4 “Interrupt Handling” on page 95
Section 8.4.4 “Interrupt
for details.
AT86RF231
Table 6-9 on page
Section
7.2.3.5
7.1.2.3
9.5.4
9.3.3
8.4.4
8.5.4
7.1.3
7.1.3
7.1.3
9.7.5
9.7.5
29