ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 117

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

9.6.3
9.6.4
8111C–MCU Wireless–09/09
External Reference Frequency Setup
Master Clock Signal Output (CLKM)
To calculate the total load capacitance, the following formula can be used:
C
The trimming capacitors provide the possibility of reducing frequency deviations caused by pro-
duction process variations or by external components tolerances. Note that the oscillation
frequency can only be reduced by increasing the trimming capacitance. The frequency deviation
caused by one step of C
An amplitude control circuit is included to ensure stable operation under different operating con-
ditions and for different crystal types. Enabling the crystal oscillator in P_ON state and after
leaving SLEEP state causes a slightly higher current during the amplitude build-up phase to
guarantee a short start-up time. At stable operation, the current is reduced to the amount neces-
sary for a robust operation. This also keeps the drive level of the crystal low.
Generally, crystals with a higher load capacitance are less sensitive to parasitic pulling effects
caused by external component variations or by variations of board and circuit parasitics. On the
other hand, a larger crystal load capacitance results in a longer start-up time and a higher steady
state current consumption.
When using an external reference frequency, the signal must be connected to pin 26 (XTAL1) as
indicated in
XOSC_CTRL) need to be set to the external oscillator mode. The oscillation peak-to-peak ampli-
tude shall be between 100 mV and 500 mV, the optimum range is between 400 mV and 500 mV.
Pin 25 (XTAL2) should not be wired.
Figure 9-8.
The generated reference clock signal can be fed to a microcontroller using pin 17 (CLKM). The
internal 16 MHz raw clock can be divided by an internal prescaler. Thus, clock frequencies of
16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 250 kHz, or 62.5 kHz can be supplied by pin CLKM.
The CLKM frequency, update scheme, and pin driver strength is configurable using register
0x03 (TRX_CTRL_0). There are two possibilities how a CLKM frequency change gets effective.
If CLKM_SHA_SEL = 0 and/or CLKM_CTRL = 0, changing the register bits CLKM_CTRL imme-
diately affects the CLKM clock rate. Otherwise (CLKM_SHA_SEL = 1 and CLKM_CTRL > 0
before changing the register bits CLKM_CTRL) the new clock rate is supplied when leaving the
SLEEP state the next time.
To reduce power consumption and spurious emissions, it is recommended to turn off the CLKM
clock when not in use or to reduce its driver strength to a minimum, refer to
Pins” on page
L
= 0.5 * (CX + C
Figure 9-8 on page 117
7.
Setup for Using an External Frequency Reference
TRIM
+ C
TRIM
PAR
decreases with increasing crystal load capacitor values.
).
XTAL1
and the register bits XTAL_MODE (register 0x12,
16 MHz
XTAL2
AT86RF231
PCB
AT86RF231
Section 1.3 “Digital
117