ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 107

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

9.3
9.3.1
8111C–MCU Wireless–09/09
Frame Buffer
Data Management
The AT86RF231 contains a 128 byte dual port SRAM. One port is connected to the SPI inter-
face, the other to the internal transmitter and receiver modules. For data communication, both
ports are independent and simultaneously accessible.
The Frame Buffer uses the address space 0x00 to 0x7F for RX and TX operation of the radio
transceiver and can keep one IEEE 802.15.4 RX or one TX frame of maximum length at a time.
Frame Buffer access modes are described in
Frame Buffer access conflicts are indicated by an under run interrupt IRQ_6 (TRX_UR). Note
that this interrupt also occurs on the attempt to write frames longer than 127 octets to the Frame
Buffer. In that case the content of the Frame Buffer cannot be guaranteed.
Frame Buffer access is only possible if the digital voltage regulator is turned on. This is valid in
all device states except in SLEEP state. An access in P_ON state is possible if pin 17 (CLKM)
provides the 1 MHz master clock.
Data in Frame Buffer (received data or data to be transmitted) remains valid as long as:
By default there is no protection of the Frame Buffer against overwriting. Therefore, if a frame is
received during Frame Buffer read access of a previously received frame, interrupt IRQ_6
(TRX_UR) is issued and the stored data might be overwritten.
Even so, the old frame data can be read, if the SPI data rate is higher than the effective over air
data rate. For a data rate of 250 kb/s a minimum SPI clock rate of 1 MHz is recommended.
Finally the microcontroller should check the transferred frame data integrity by an FCS check.
To protect the Frame Buffer content against being overwritten by newly incoming frames the
radio transceiver state should be changed to PLL_ON state after reception. This can be
achieved by writing immediately the command PLL_ON to register bits TRX_CMD (register
0x02, TRX_STATE) after receiving the frame, indicated by IRQ_3 (TRX_END).
Alternatively Dynamic Frame Buffer Protection can be used to protect received frames against
overwriting, for details refer to
Both procedures do not protect the Frame Buffer from overwriting by the microcontroller.
In Extended Operating Mode during TX_ARET operation, see
Transmit with Automatic Retry and CSMA-CA Retry” on page
to receive, if an acknowledgement of a previously transmitted frame was requested. During this
period received frames are evaluated, but not stored in the Frame Buffer. This allows the radio
transceiver to wait for an acknowledgement frame and retry the frame transmission without writ-
ing them again.
A radio transceiver state change, except a transition to SLEEP state or a reset, does not affect
the Frame Buffer contents. If the radio transceiver is forced into SLEEP, the Frame Buffer is
powered off and the stored data gets lost.
• No new frame or other data are written into the buffer over SPI
• No new frame is received (in any BUSY_RX state)
• No state change into SLEEP state is made
• No RESET took place
Section 11.8 “Dynamic Frame Buffer Protection” on page
Section 6.6.2 “Register Description” on page
64, the radio transceiver switches
Section 7.2.4 “TX_ARET_ON -
AT86RF231
154.
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30.