ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 145
ATmega1284PR231
Manufacturer Part Number
ATmega1284PR231
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT86RF231.pdf
(198 pages)
2.ATMEGA1284PR231.pdf
(380 pages)
3.ATMEGA1284PR231.pdf
(20 pages)
Specifications of ATmega1284PR231
Flash (kbytes)
128 Kbytes
Max. Operating Frequency
20 MHz
Max I/o Pins
32
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
16
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
3
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
2
Antenna Diversity
Yes
External Pa Control
Yes
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
13.2
Transmit Current Consumption (ma)
14.4
Link Budget (dbm)
104
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8111C–MCU Wireless–09/09
Table 11-12. Antenna Diversity Control
Note:
• Bit 2 - ANT_EXT_SW_EN
If enabled, pin 9 (DIG1) and pin 10 (DIG2) become output pins and provide a differential control
signal for an Antenna Diversity switch. The selection of a specific antenna is done either by the
automated Antenna Diversity algorithm (ANT_DIV_EN = 1), or according to register bits
ANT_CTRL if Antenna Diversity algorithm is disabled.
Do not enable Antenna Diversity RF switch control (ANT_EXT_SW_EN = 1) and RX Frame
Time Stamping (IRQ_2_EXT_EN = 1) at the same time, see
Stamping” on page
If the register bit is set the control pins DIG1/DIG2 are activated in all radio transceiver states as
long as register bit ANT_EXT_SW_EN is set. If the AT86RF231 is not in a receive or transmit
state, it is recommended to disable register bit ANT_EXT_SW_EN to reduce the power con-
sumption or avoid leakage current of an external RF switch, especially during SLEEP state. If
register bit ANT_EXT_SW_EN = 0, output pins DIG1 and DIG2 are pulled-down to digital
ground.
Table 11-13. Antenna Diversity RF Switch Enable
Note:
• Bit [1:0] - ANT_CTRL
These register bits provide a static control of an Antenna Diversity switch. Setting
ANT_DIV_EN = 0 (Antenna Diversity disabled), this register setting defines the selected
antenna. Although it is possible to change register bits ANT_CTRL in state TRX_OFF, this
change will be effective at pins DIG1 and DIG2 in state PLL_ON as well as all receive and trans-
mit states.
Table 11-14. Antenna Diversity Switch Control
Register Bit
ANT_DIV_EN
Register Bit
ANT_EXT_SW_EN
Register Bit
If ANT_DIV_EN = 1 register bit ANT_EXT_SW_EN shall be set to 1, too. This is not automatically
done by the hardware.
If ANT_EXT_SW_EN = 0, register bit ANT_DIV_EN shall be set to 0 and register bits ANT_CTRL
to 3. This is not automatically done by the hardware.
Value
150.
Value
Value
0
1
0
1
Description
Description
Antenna Diversity algorithm disabled
Antenna Diversity algorithm enabled
Description
Antenna Diversity RF Switch Control disabled
Antenna Diversity RF Switch Control enabled
Section 11.6 “RX Frame Time
AT86RF231
145
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