LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 10

• Manufacturer Part Number: LM3S3768
• Description: Lm3s3768 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Figure 15-9.
Figure 15-10. MICROWIRE Frame Format (Single Frame) .................................................................... 437
Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 438
Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 438
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 16-4.
Figure 16-5.
Figure 16-6.
Figure 16-7.
Figure 16-8.
Figure 16-9.
Figure 16-10. Master Burst RECEIVE .................................................................................................. 476
Figure 16-11. Master Burst RECEIVE after Burst SEND ........................................................................ 477
Figure 16-12. Master Burst SEND after Burst RECEIVE ........................................................................ 478
Figure 16-13. Slave Command Sequence ............................................................................................ 479
Figure 17-1.
Figure 18-1.
Figure 18-2.
Figure 18-3.
Figure 19-1.
Figure 19-2.
Figure 19-3.
Figure 19-4.
Figure 19-5.
Figure 19-6.
Figure 20-1.
Figure 20-2.
Figure 21-1.
Figure 24-1.
Figure 24-2.
Figure 24-3.
Figure 24-4.
Figure 24-5.
Figure 24-6.
Figure 24-7.
Figure 24-8.
Figure 24-9.
Figure 24-10. Power-On Reset Timing ................................................................................................. 704
Figure 24-11. Brown-Out Reset Timing ................................................................................................ 704
Figure 24-12. Software Reset Timing ................................................................................................... 704
Figure 24-13. Watchdog Reset Timing ................................................................................................. 704
Figure 25-1.
10
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 436
I
I
START and STOP Conditions ......................................................................................... 469
Complete Data Transfer with a 7-Bit Address ................................................................... 470
R/S Bit in First Byte ........................................................................................................ 470
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 473
Master Single RECEIVE ................................................................................................. 474
Master Burst SEND ....................................................................................................... 475
USB Module Block Diagram ........................................................................................... 503
Analog Comparator Module Block Diagram ..................................................................... 593
Structure of Comparator Unit .......................................................................................... 594
Comparator Internal Reference Structure ........................................................................ 595
PWM Unit Diagram ........................................................................................................ 605
PWM Module Block Diagram .......................................................................................... 606
PWM Count-Down Mode ................................................................................................ 607
PWM Count-Up/Down Mode .......................................................................................... 607
PWM Generation Example In Count-Up/Down Mode ....................................................... 608
PWM Dead-Band Generator ........................................................................................... 608
QEI Block Diagram ........................................................................................................ 659
Quadrature Encoder and Velocity Predivider Operation .................................................... 661
100-Pin LQFP Package Pin Diagram .............................................................................. 676
Load Conditions ............................................................................................................ 696
I
Hibernation Module Timing ............................................................................................. 700
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 700
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 701
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 701
JTAG Test Clock Input Timing ......................................................................................... 702
JTAG Test Access Port (TAP) Timing .............................................................................. 702
External Reset Timing (RST) .......................................................................................... 703
100-Pin LQFP Package .................................................................................................. 705
2
2
2
C Block Diagram ......................................................................................................... 468
C Bus Configuration .................................................................................................... 469
C Timing ..................................................................................................................... 699
Preliminary
2
C Bus ............................................................... 470
June 02, 2008