LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 566

• Manufacturer Part Number: LM3S3768
• Description: Lm3s3768 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Type
Univeral Serial Bus (USB) Controller
USBRXCSRLn Host Mode
USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1)
Base 0x4005.0000
Offset 0x116
Type R/W, reset 0x00
566
Host
Device
Bit/Field
CLRDT
W1S
7
6
5
4
7
0
STALLED
R/W0C
Register 63: USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1),
offset 0x116
Register 64: USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2),
offset 0x126
Register 65: USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3),
offset 0x136
USBRXCSRLn is an 8-bit register that provides control and status bits for transfers through the
currently selected receive endpoint.
6
0
REQPKT
R/W
STALLED
REQPKT
5
0
CLRDT
FLUSH
Name
FLUSH
W1S
4
0
DATAERR /
R/W0C
NAKTO
3
0
R/W0C
Type
W1S
W1S
R/W
ERROR
R/W0C
2
0
FULL
RO
Reset
1
0
0
0
0
0
RXRDY
Preliminary
R/W0C
0
0
Description
Clear Data Toggle
The CPU writes a 1 to this bit to reset the endpoint data toggle to 0.
Endpoint Stalled
When a STALL handshake is received, this bit is set and an interrupt is
generated. The CPU should clear this bit.
Request Packet
The CPU writes a 1 to this bit to request an IN transaction. It is cleared
when RXRDY is set.
Flush FIFO
The CPU writes a 1 to this bit to flush the next packet to be read from
the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit
is cleared.
Note:
FLUSH should only be used when RXRDY is set. At other times,
it may cause data to be corrupted. Also note that, if the FIFO
is double-buffered, FLUSH may need to be set twice to
completely clear the FIFO.
June 02, 2008