LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 439

• Manufacturer Part Number: LM3S3768
• Description: Lm3s3768 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

15.3
June 02, 2008
are used for SSI operation and DMA is enabled, the SSI interrupt handler must be designed to
handle the μDMA completion interrupt.
See “Micro Direct Memory Access (μDMA)” on page 189 for more details about programming the
μDMA controller.
Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:
1.
2.
3.
4.
5.
6.
As an example, assume the SSI must be configured to operate with the following parameters:
■
■
■
■
Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=2, SCR must be 9.
Master operation
Freescale SPI mode (SPO=1, SPH=1)
1 Mbps bit rate
8 data bits
Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.
Select whether the SSI is a master or slave:
a.
b.
c.
Configure the clock prescale divisor by writing the SSICPSR register.
Write the SSICR0 register with the following configuration:
■
■
■
■
Optionally, configure the uDMA channel (see “Micro Direct Memory Access (μDMA)” on page 189)
and enable the DMA option(s) in the SSIDMACTL register.
Enable the SSI by setting the SSE bit in the SSICR1 register.
Serial clock rate (SCR)
Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
The data size (DSS)
For master operations, set the SSICR1 register to 0x0000.0000.
For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
Preliminary
LM3S3768 Microcontroller
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