LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 379

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LM3S3768

Manufacturer Part Number
LM3S3768
Description
Lm3s3768 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
Reset
Reset
Type
Type
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0)
Base 0x4003.8000
Offset 0x048
Type RO, reset 0x0000.0000
June 02, 2008
Bit/Field
31:10
9:0
RO
RO
31
15
0
0
RO
RO
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset
0x0A8
This register contains the conversion results for samples collected with the Sample Sequencer (the
ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1,
ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return
conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the
FIFO is not properly handled by software, overflow and underflow conditions are registered in the
ADCOSTAT and ADCUSTAT registers.
30
14
0
0
RO
RO
29
13
reserved
0
0
Name
reserved
DATA
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0x00
0x00
0
9
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Conversion Result Data
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
DATA
RO
RO
20
0
4
0
RO
RO
19
0
3
0
LM3S3768 Microcontroller
RO
RO
18
0
2
0
RO
RO
17
0
1
0
RO
RO
16
0
0
0
379

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