LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 275

• Manufacturer Part Number: LM3S3768
• Description: Lm3s3768 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
GPIO Pull-Up Select (GPIOPUR)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x510
Type R/W, reset -
June 02, 2008
Bit/Field
31:8
7:0
RO
RO
31
15
0
0
RO
RO
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up
resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 276). Write access
to this register is protected with the GPIOCR register. Bits in GPIOCR that are set to 0 will prevent
writes to the equivalent bit in this register.
Note:
30
14
0
0
RO
RO
29
13
reserved
0
0
Name
The commit control registers provide a layer of protection against accidental programming
of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function
Select (GPIOAFSEL) register (see page 269), GPIO Pull-Up Select (GPIOPUR) register
(see page 275), and GPIO Digital Enable (GPIODEN) register (see page 278) are not
committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 280) has been
unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 281)
have been set to 1.
PUE
RO
RO
28
12
0
0
reserved
RO
RO
27
11
0
0
Type
R/W
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0x00
0
9
0
-
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Pad Weak Pull-Up Enable
A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n]
enables. The change is effective on the second clock cycle after the
write.
Note:
R/W
RO
23
0
7
-
The default reset value for the GPIOAFSEL, GPIOPUR, and
GPIODEN registers are 0x0000.0000 for all GPIO pins, with
the exception of the four JTAG/SWD pins (PC[3:0]). These
four pins default to JTAG/SWD functionality. Because of this,
the default reset value of these registers for Port C is
0x0000.000F.
R/W
RO
22
0
6
-
R/W
RO
21
0
5
-
R/W
RO
20
0
4
-
PUE
R/W
RO
19
0
3
-
LM3S3768 Microcontroller
R/W
RO
18
0
2
-
R/W
RO
17
0
1
-
R/W
RO
16
0
0
-
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