LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 573

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LM3S3768

Manufacturer Part Number
LM3S3768
Description
Lm3s3768 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
June 02, 2008
Bit/Field
2:1
3
0
DMAMOD
reserved
INCRX
Name
R/W0C
Type
R/W
RO
Reset
0x00
0
0
Preliminary
Description
DMA Request Mode
The CPU sets this bit to select DMA Request Mode 1 and clears it to
select DMA Request Mode 0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Incomplete Receive
This bit is set in a high-bandwidth isochronous/interrupt transfer if the
packet in the receive FIFO is incomplete because parts of the data were
not received. It is cleared when RXRDY is cleared.
Note:
Only valid for isochronous transfers.
LM3S3768 Microcontroller
573

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