LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 641
LM3S3768
Manufacturer Part Number
LM3S3768
Description
Lm3s3768 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S3768.pdf
(755 pages)
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Reset
Reset
Type
Type
PWM0 Counter (PWM0COUNT)
Base 0x4002.8000
Offset 0x054
Type RO, reset 0x0000.0000
June 02, 2008
Bit/Field
31:16
15:0
RO
RO
31
15
0
0
RO
RO
Register 31: PWM0 Counter (PWM0COUNT), offset 0x054
Register 32: PWM1 Counter (PWM1COUNT), offset 0x094
Register 33: PWM2 Counter (PWM2COUNT), offset 0x0D4
Register 34: PWM3 Counter (PWM3COUNT), offset 0x114
These registers contain the current value of the PWM counter. When this value matches the load
register, a pulse is output; this can drive the generation of a PWM signal (via the
PWMnGENA/PWMnGENB registers, see page 644 and page 647) or drive an interrupt or ADC trigger
(via the PWMnINTEN register, see page 636). A pulse with the same capabilities is generated when
this value is zero.
30
14
0
0
RO
RO
29
13
reserved
0
0
Name
Count
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0x00
0x00
0
9
0
Preliminary
RO
RO
24
0
8
0
reserved
Count
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Counter Value
The current value of the counter.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
LM3S3768 Microcontroller
RO
RO
18
0
2
0
RO
RO
17
0
1
0
RO
RO
16
0
0
0
641
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