LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 220

• Manufacturer Part Number: LM3S3768
• Description: Lm3s3768 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Micro Direct Memory Access (μDMA)
DMA Channel Control Base Pointer (DMACTLBASE)
Base 0x400F.F000
Offset 0x008
Type R/W, reset 0x0000.0000
220
Bit/Field
31:10
9:0
R/W
R/W
31
15
0
0
R/W
R/W
Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008
The DMACTLBASE register must be configured so that the base pointer points to a location in
system memory.
The amount of system memory that you must assign to the controller depends on the number of
DMA channels used and whether you configure it to use the alternate channel control data structure.
See “Channel Configuration” on page 192 for details about the Channel Control Table. The base
address must be aligned on a 1024-byte boundary. You cannot read this register when the controller
is in the reset state.
30
14
0
0
R/W
R/W
29
13
reserved
0
0
ADDR
Name
ADDR
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
Type
R/W
RO
R/W
R/W
26
10
0
0
R/W
RO
Reset
25
0x00
0x00
0
9
0
Preliminary
R/W
RO
24
0
8
0
ADDR
Description
Channel Control Base Address
Pointer to the base address of the channel control table. The base
address must be 1024-byte aligned.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
reserved
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
R/W
RO
17
0
1
0
June 02, 2008
R/W
RO
16
0
0
0