LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 514

• Manufacturer Part Number: LM3S3768
• Description: Lm3s3768 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Univeral Serial Bus (USB) Controller
17.2.3.3 Host Negotiation
17.3
17.3.1
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detected, then the USB controller is the A device. It generates a Session Request interrupt to indicate
that the B device is requesting a session. The SESSION bit in the USBDEVCTL register should then
be set to start a session.
When the USB controller is the A device, ID is Low, and it automatically enters Host mode when a
session starts. When the USB controller is the B device, ID is High, and it automatically enters
Device mode when a session starts. However, the CPU can request that the USB controller become
the host by setting the HOSTREQ bit in the USBDEVCTL register. This bit can be set either at the
same time as requesting a Session Start by setting the SESSION bit in the USBDEVCTL register,
or at any time after a session has started. When the USB controller next enters Suspend mode,
assuming the HOSTREQ bit remains set, it enters Host mode and begins host negotiation (as specified
in the USB On-The-Go supplement) by causing the PHY to disconnect the pull-up resistor on the
D+ line. This causes the A device to switch to Device mode and connect its own pull-up resistor.
When the USB controller detects this, it generates a Connect interrupt. It also sets the RESET bit in
the USBPOWER register to begin resetting the A device. The USB controller begins this reset
sequence automatically to ensure that reset is started as required within 1 ms of the A device
connecting its pull-up resistor. The main processor should wait at least 20 ms, then clear the RESET
bit and enumerate the A device.
When the USB OTG controller B device has finished using the bus, it goes into Suspend mode by
setting the SUSPEND bit in the USBPOWER register. The A device detects this and either terminates
the session or reverts to Host mode. If the A device is USB OTG controller, it generates a Disconnect
interrupt.
Initialization and Configuration
The initial configuration in all cases requires that the processor enable the USB controller before
setting any registers. The next step is to enable the USB PLL so that the correct clocking is provided
to the USB controller’s physical layer interface (PHY). To ensure that voltage is not supplied to the
bus incorrectly, the external power control signal, USB0EPEN, should be de-asserted on start up.
This requires setting the USB0EPEN and USB0PFLT pins to be controlled by the USB controller and
not have their default GPIO behavior.
The VBUS sense and ID pins (USB0VBUS and USB0ID) do not require any configuration as they
are dedicated pins for the USB controller. In OTG mode, these pins directly connect to the USB
connector's VBUS and ID signals. In Host and Device modes, these pins must be tied to appropriate
voltage levels. USB0VBUS must be tied to 5 V (4.75-5.25V). USB0ID must be tied Low for USB Host
operation or tied High for USB Device Operation. These pins should not be used as GPIOs while
using the USB controller as it may cause unexpected behavior in the controller.
Pin Configuration
When using the device controller portion of the USB controller in a system that also provides host
functionality, the power to VBUS must be disabled to allow the external host controller to supply
power. Usually, the USB0EPEN signal is used to control the external regulator and should be
de-asserted to avoid having two devices driving the USB0VBUS power pin on the USB connector.
When the USB controller is acting as a host, it is in control of two signals that are attached to an
external voltage supply that provides power to VBUS. The host controller uses the USB0EPEN signal
to enable or disable power to the USB0VBUS pin on the USB connector. There is also an input pin,
USB0PFLT, which provides feedback when there has been a power fault on VBUS. The USB0PFLT
signal can be configured to either automatically de-assert the USB0EPEN signal to disable power,
and/or it can generate an interrupt to the main processor to allow it to handle the power fault condition.
Preliminary
June 02, 2008