LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 508

• Manufacturer Part Number: LM3S3768
• Description: Lm3s3768 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Univeral Serial Bus (USB) Controller
17.2.1.6 Device Mode Suspend
17.2.1.7 Start-of-Frame
508
Stalled Control Transfer
The USB controller automatically issues a STALL handshake to a control transfer under the following
conditions:
1.
2.
3.
4.
Zero Length OUT Data Packets
A zero-length OUT data packet is used to indicate the end of a control transfer. In normal operation,
such packets should only be received after the entire length of the device request has been
transferred.
However, if the host sends a zero-length OUT data packet before the entire length of device request
has been transferred, it is signaling the premature end of the transfer. In this case, the USB controller
automatically flushes any IN token ready for the data phase from the FIFO and sets the SETUP bit
in the USBCSRL0 register.
When no activity has occurred on the USB bus for 3 ms, the USB controller automatically enters
Suspend mode. If the Suspend interrupt has been enabled, an interrupt is generated at this time.
When in Suspend mode, the PHY also goes into Suspend mode. When Resume signaling is detected,
the USB controller exits Suspend mode and takes the PHY out of Suspend. If the Resume interrupt
is enabled, an interrupt is generated. The USB controller can also be forced to exit Suspend mode
by setting the RESUME bit in the USBPOWER register. When this bit is set, the USB controller exits
Suspend mode and drives Resume signaling onto the bus. The RESUME bit is cleared after 10 ms
(a maximum of 15 ms) to end Resume signaling.
To meet USB power requirements, the controller can be put into Deep Sleep. This keeps the controller
in a static state. The USB controller is not able to Hibernate since this will cause all the internal
states to be lost.
When the USB controller is operating in device mode, it receives a Start-Of-Frame packet from the
host once every millisecond. When the SOF packet is received, the 11-bit frame number contained
in the packet is written into the USBFRAME register and an SOF interrupt is also signaled and can
be handled by the application. Once the USB controller has started to receive SOF packets, it
expects one every millisecond. If no SOF packet is received after 1.00358 ms, it is assumed that
the packet has been lost and the USBFRAME register is not updated. The USB controller continues
and resynchronizes these pulses to the received SOF packets when these packets are successfully
received again.
The host sends more data during an OUT data phase of a control transfer than was specified
in the device request during the SETUP phase. This condition is detected by the USB controller
when the host sends an OUT token (instead of an IN token) after the last OUT packet has been
unloaded and the DATAEND bit in the USBCSRL0 register has been set.
The host requests more data during an IN data phase of a control transfer than was specified
in the device request during the SETUP phase. This condition is detected by the USB controller
when the host sends an IN token (instead of an OUT token) after the CPU has cleared TXRDY
and set DATAEND in response to the ACK issued by the host to what should have been the last
packet.
The host sends more than USBRXMAXPn bytes of data with an OUT data token.
The host sends more than a zero length data packet for the OUT status phase.
Preliminary
June 02, 2008