LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 262

• Manufacturer Part Number: LM3S3768
• Description: Lm3s3768 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
General-Purpose Input/Outputs (GPIOs)
GPIO Interrupt Both Edges (GPIOIBE)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x408
Type R/W, reset 0x0000.0000
262
Bit/Field
31:8
7:0
RO
RO
31
15
0
0
RO
RO
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO
Interrupt Sense (GPIOIS) register (see page 261) is set to detect edges, bits set to High in GPIOIBE
configure the corresponding pin to detect both rising and falling edges, regardless of the
corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 263). Clearing a bit
configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset.
30
14
0
0
RO
RO
29
13
reserved
0
0
Name
IBE
RO
RO
28
12
0
0
reserved
RO
RO
27
11
0
0
Type
R/W
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0x00
0x00
0
9
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Interrupt Both Edges
The IBE values are defined as follows:
Value
0
1
R/W
RO
23
0
7
0
Description
Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register (see page 263).
Both edges on the corresponding pin trigger an interrupt.
Note:
R/W
RO
22
0
6
0
Single edge is determined by the corresponding bit
in GPIOIEV.
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
IBE
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
R/W
RO
17
0
1
0
June 02, 2008
R/W
RO
16
0
0
0