LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 208

• Manufacturer Part Number: LM3S3768
• Description: Lm3s3768 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Micro Direct Memory Access (μDMA)
9.3.4.3
9.3.4.4
9.3.4.5
208
Table 9-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive Example
Note:
Configure the Peripheral Interrupt
In order to use μDMA Ping-Pong mode, it is best to use an interrupt handler. (It is also possible to
use ping-pong mode without interrupts by polling). The interrupt handler will be triggered after each
buffer is complete.
1.
Enable the μDMA Channel
Now the channel is configured and is ready to start.
1.
Process Interrupts
The μDMA controller is now configured and enabled for transfer on channel 8. When the peripheral
asserts the DMA request signal, the μDMA controller will make transfers into buffer A using the
primary channel control structure. When the primary transfer to buffer A is complete, it will switch
to the alternate channel control structure and make transfers into buffer B. At the same time, the
primary channel control word mode field will be set to indicate Stopped, and an interrupt will be
triggered.
When an interrupt is triggered, the interrupt handler must determine which buffer is complete and
process the data, or set a flag that the data needs to be processed by non-interrupt buffer processing
code. Then the next buffer transfer must be set up.
In the interrupt handler:
1.
Field in DMACHCTL
DSTINC
DSTSIZE
SRCINC
SRCSIZE
reserved
ARBSIZE
XFERSIZE
NXTUSEBURST
XFERMODE
Configure and enable an interrupt handler for the peripheral.
Enable the channel by setting bit 8 of the DMA Channel Enable Set (DMAENASET) register.
Read the primary channel control word at offset 0x088 and check the XFERMODE field. If the
field is 0, this means buffer A is complete. If buffer A is complete, then:
In this example, it is not important if the peripheral makes a single request or a burst request.
Since the peripheral has a FIFO that will trigger at a level of 8, the arbitration size is set to
8. If the peripheral does make a burst request, then 8 bytes will be transferred, which is
what the FIFO can accomodate. If the peripheral makes a single request (if there is any
data in the FIFO), then one byte will be transferred at a time. If it is important to the
application that transfers only be made in bursts, then the channel useburst SET[n] bit
should be set by writing a 1 to bit 8 of the DMA Channel Useburst Set
(DMAUSEBURSTSET) register.
Preliminary
31:30
29:28
27:26
25:24
23:18
17:14
Bits
13:4
2:0
3
Value
63
0
0
3
0
0
3
0
3
Description
8-bit destination address increment
8-bit destination data size
Source address does not increment
8-bit source data size
Reserved
Arbitrates after 8 transfers
Transfer 64 items
N/A for this transfer type
Use Ping-Pong transfer mode
June 02, 2008