LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 73

• Manufacturer Part Number: LM3S3768
• Description: Lm3s3768 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

6.1.5.7
6.1.6
June 02, 2008
a system clock until the T
responsibility to have a stable clock source (like the main oscillator) before the RCC/RCC2 register
is switched to use the PLL.
If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system
control hardware continues to clock the controller from the oscillator selected by the RCC/RCC2
register until the main PLL is stable (T
can use many methods to ensure that the system is clocked from the main PLL, including periodically
polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock
interrupt.
The USB PLL is not protected during the lock time (T
the USB PLL has locked before using the interface. Software can use many methods to ensure the
T
Interrupt Status (RIS) register, and enabling the USB PLL Lock interrupt.
Main Oscillator Verification Circuit
A circuit is added to ensure that the main oscillator is running at the appropriate frequency. The
circuit monitors the main oscillator frequency and signals if the frequency is outside of the allowable
band of attached crystals.
The detection circuit is enabled using the CVAL bit in the Main Oscillator Control (MOSCCTL)
register. If this circuit is enabled and detects an error, the following sequence is performed by the
hardware:
1.
2.
3.
4.
5.
System Control
For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep
mode, respectively.
In Run mode, the processor executes code. In Sleep mode, the clock frequency of the active
peripherals is unchanged, but the processor is not clocked and therefore no longer executes code.
In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the
Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns
the device to Run mode from one of the sleep modes; the sleep modes are entered on request from
the code. Each mode is described in more detail below.
There are four levels of operation for the device defined as:
■
■
USBREADY
Run Mode. Run mode provides normal operation of the processor and all of the peripherals that
are currently enabled by the RCGCn registers. The system clock can be any of the available
clock sources including the PLL.
Sleep Mode. Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for
Interrupt) instruction. Any properly configured interrupt event in the system will bring the
The MOSCFAIL bit in the Reset Cause (RESC) register is set.
If the internal oscillator (IOSC) is disabled, it is enabled.
The system clock is switched from the main oscillator to the IOSC.
A system-wide reset is initiated that lasts for 32 IOSC periods.
Reset is de-asserted and the processor is directed to the NMI handler during the reset sequence.
period has passed, including periodically polling the the USBPLLLRIS bit in the Raw
READY
condition is met after one of the two changes above. It is the user's
Preliminary
READY
time met), after which it changes to the PLL. Software
USBREADY
) and software should ensure that
LM3S3768 Microcontroller
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