LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 473

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LM3S3768

Manufacturer Part Number
LM3S3768
Description
Lm3s3768 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
16.2.4
16.2.5
16.2.5.1 I
June 02, 2008
Loopback Operation
The I
is accomplished by setting the LPBK bit in the I
loopback mode, the SDA and SCL signals from the master and slave modules are tied together.
Command Sequence Flow Charts
This section details the steps required to perform the various I
slave mode.
The figures that follow show the command sequences available for the I
Figure 16-7. Master Single SEND
2
C Master Command Sequences
Error Service
2
C modules can be placed into an internal loopback mode for diagnostic or debug work. This
NO
NO
NO
BUSBSY bit=0?
ERROR bit=0?
Read I2CMCS
Read I2CMCS
Write ---0-111 to
Write data to
BUSY bit=0?
Write Slave
Address to
I2CMDR
I2CMCS
I2CMSA
Idle
Idle
YES
YES
YES
Single Master
omitted in a
Sequence
Preliminary
may be
system
2
C Master Configuration (I2CMCR) register. In
2
C transfer types in both master and
2
LM3S3768 Microcontroller
C master.
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