LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 631

• Manufacturer Part Number: LM3S3768
• Description: Lm3s3768 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
PWM0 Control (PWM0CTL)
Base 0x4002.8000
Offset 0x040
Type R/W, reset 0x0000.0000
June 02, 2008
Bit/Field
31:19
R/W
RO
31
15
0
0
DBFallUpd
R/W
RO
Register 11: PWM0 Control (PWM0CTL), offset 0x040
Register 12: PWM1 Control (PWM1CTL), offset 0x080
Register 13: PWM2 Control (PWM2CTL), offset 0x0C0
Register 14: PWM3 Control (PWM3CTL), offset 0x100
These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM generator
0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable
mode are all controlled via these registers. The blocks produce the PWM signals, which can be
either two independent PWM signals (from the same counter), or a paired set of PWM signals with
dead-band delays added.
The PWM0 block produces the PWM0 and PWM1 outputs, the PWM1 block produces the PWM2 and
PWM3 outputs, the PWM2 block produces the PWM4 and PWM5 outputs, and the PWM3 block produces
the PWM6 and PWM7 outputs.
30
14
0
0
R/W
RO
29
13
reserved
0
DBRiseUpd
0
Name
R/W
RO
28
12
0
0
R/W
RO
27
11
0
0
DBCtlUpd
Type
RO
R/W
RO
26
10
0
0
reserved
R/W
RO
Reset
25
0x00
0
9
0
GenBUpd
Preliminary
R/W
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
RO
23
0
7
0
GenAUpd
R/W
RO
22
0
6
0
CmpBUpd
R/W
RO
21
0
5
0
CmpAUpd
R/W
RO
20
0
4
0
LoadUpd
R/W
RO
19
0
3
0
LM3S3768 Microcontroller
LATCH
Debug
R/W
R/W
18
0
2
0
MINFLTPER
Mode
R/W
R/W
17
0
1
0
FLTSRC
Enable
R/W
R/W
16
0
0
0
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