LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 511

• Manufacturer Part Number: LM3S3768
• Description: Lm3s3768 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

17.2.2.3 Out Transactions as a Host
17.2.2.4 Transaction Scheduling
June 02, 2008
the device. When there is a known number of packets to be transferred, the USBRQPKTCOUNTn
register associated with the endpoint should be set to the number of packets to be transferred. The
USB controller decrements the value in the USBRQPKTCOUNTn register following each request.
When the USBRQPKTCOUNTn value decrements to 0, the AUTORQ bit is cleared to prevent any
further transactions being attempted. For cases where the size of the transfer is unknown,
USBRQPKTCOUNTn should be left set to zero. AUTORQ then remains set until cleared by the
reception of a short packet (that is, less than MaxP) such as may occur at the end of a bulk transfer.
If the device responds to a bulk or interrupt IN token with a NAK, the USB host controller keeps
retrying the transaction until any NAK Limit that has been set has been reached. If the target device
responds with a STALL, however, the USB host controller does not retry the transaction but interrupts
the CPU with the STALLED bit in the USBCSRL0 register set. If the target device does not respond
to the IN token within the required time, or there was a CRC or bit-stuff error in the packet, the USB
host controller retries the transaction. If after three attempts the target device has still not responded,
the USB host controller clears the REQPKT bit and interrupts the CPU by setting the ERROR bit in
the USBCSRL0 register.
OUT transactions are handled in a similar manner to the way in which IN transactions are handled
when the USB controller is in Device mode. The TXRDY bit in the USBTXCSRLn register needs to
be set as each packet is loaded into the transmit FIFO. Again, setting the AUTOSET bit in the
USBTXCSRHn register automatically sets TXRDY when a maximum-sized packet has been loaded
into the FIFO. Furthermore, AUTOSET can be used with a DMA controller to perform complete bulk
transfers without software intervention.
If the target device responds to the OUT token with a NAK, the USB host controller keeps retrying
the transaction until the NAK Limit that has been set has been reached. However, if the target device
responds with a STALL, the USB controller does not retry the transaction but interrupts the main
processor by setting the STALLED bit in the USBTXCSRLn register. If the target device does not
respond to the OUT token within the required time, or there was a CRC or bit-stuff error in the packet,
the USB host controller retries the transaction. If after three attempts the target device has still not
responded, the USB controller flushes the FIFO and interrupts the main processor by setting the
ERROR bit in the USBTXCSRLn register.
Scheduling of transactions is handled automatically by the USB host controller. The host controller
allows configuration of the endpoint communication scheduling based on the type of endpoint
transaction. Interrupt transactions can be scheduled to occur in the range of every frame to every
255 frames in 1 frame increments. Bulk endpoints do not allow scheduling parameters, but do allow
for a NAK timeout in the event an endpoint on a device is not responding. Isochronous endpoints
can be scheduled from every frame to every 2
The USB controller maintains a frame counter. If the target device is a full-speed device, the USB
controller automatically sends an SOF packet at the start of each frame and increments the frame
counter. If the target device is a low-speed device, a ‘K’ state is transmitted on the bus to act as a
“keep-alive” to stop the low-speed device from going into Suspend mode.
After the SOF packet has been transmitted, the USB host controller cycles through all the configured
endpoints looking for active transactions. An active transaction is defined as a receive endpoint for
which the REQPKT bit is set or a transmit endpoint for which the TXRDY bit and/or the FIFONE bit is
set.
An active isochronous or interrupt transaction starts only if it is found on the first transaction scheduler
cycle of a frame and if the interval counter for that endpoint has counted down to zero. This ensures
Preliminary
16
frames, in powers of 2.
LM3S3768 Microcontroller
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