LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 336

• Manufacturer Part Number: LM3S3768
• Description: Lm3s3768 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Watchdog Timer
Watchdog Control (WDTCTL)
Base 0x4000.0000
Offset 0x008
Type R/W, reset 0x0000.0000
336
Bit/Field
31:2
RO
RO
1
0
31
15
0
0
RO
RO
Register 3: Watchdog Control (WDTCTL), offset 0x008
This register is the watchdog control register. The watchdog timer can be configured to generate a
reset signal (on second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled, all subsequent writes to the control register are
ignored. The only mechanism that can re-enable writes is a hardware reset.
30
14
0
0
RO
RO
29
13
reserved
0
0
RESEN
INTEN
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
R/W
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0x00
0
9
0
reserved
0
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Reset Enable
The RESEN values are defined as follows:
Watchdog Interrupt Enable
The INTEN values are defined as follows:
Value
Value
0
1
0
1
RO
RO
23
0
7
0
Description
Disabled.
Enable the Watchdog module reset output.
Description
Interrupt event disabled (once this bit is set, it can only be
cleared by a hardware reset).
Interrupt event enabled. Once enabled, all writes are ignored.
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
RESEN
R/W
RO
17
0
1
0
June 02, 2008
INTEN
R/W
RO
16
0
0
0