LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 673

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LM3S3768

Manufacturer Part Number
LM3S3768
Description
Lm3s3768 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
Reset
Reset
Type
Type
QEI Interrupt Enable (QEIINTEN)
QEI0 base: 0x4002.C000
Offset 0x020
Type R/W, reset 0x0000.0000
June 02, 2008
Bit/Field
31:4
RO
RO
3
2
1
0
31
15
0
0
RO
RO
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020
This register contains enables for each of the QEI module’s interrupts. An interrupt is asserted to
the controller if its corresponding bit in this register is set to 1.
30
14
0
0
RO
RO
29
13
reserved
0
0
IntTimer
IntIndex
IntError
Name
IntDir
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
R/W
R/W
R/W
RO
RO
RO
26
10
0
0
reserved
RO
RO
Reset
25
0x00
0
9
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Phase Error Interrupt Enable
When 1, an interrupt occurs when a phase error is detected.
Direction Change Interrupt Enable
When 1, an interrupt occurs when the direction changes.
Timer Expires Interrupt Enable
When 1, an interrupt occurs when the velocity timer expires.
Index Pulse Detected Interrupt Enable
When 1, an interrupt occurs when the index pulse is detected.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
IntError
R/W
RO
19
0
3
0
LM3S3768 Microcontroller
IntDir
R/W
RO
18
0
2
0
IntTimer
R/W
RO
17
0
1
0
IntIndex
R/W
RO
16
0
0
0
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